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authorNitin Garg <nitin.garg@freescale.com>2015-03-27 14:45:43 -0500
committerYe Li <ye.li@nxp.com>2017-04-05 14:04:34 +0800
commit4fbf9514fd56ea622fb696925b6cdfe3d78a6ba2 (patch)
tree1da55c44402cd8676c141bfa78e5feac399d19d2 /arch/arm/include
parent4b8cd55c465fb231ad64d4df704510d8eb8b6863 (diff)
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MLK-10496: Check the PL310 version for applying errata
Apply errata based on PL310 version instead of compile time. Also set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> (cherry picked from commit 31751fa9cf29ef4056f49fe06a54700a89c9bdc5)
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/pl310.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
index d588f94..6f79178 100644
--- a/arch/arm/include/asm/pl310.h
+++ b/arch/arm/include/asm/pl310.h
@@ -3,6 +3,8 @@
* Texas Instruments, <www.ti.com>
* Aneesh V <aneesh@ti.com>
*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PL310_H_
@@ -79,4 +81,9 @@ void pl310_clean_inval_all(void);
void pl310_inval_range(u32 start, u32 end);
void pl310_clean_inval_range(u32 start, u32 end);
+#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
+#define L2X0_CACHE_ID_PART_L310 (3 << 6)
+#define L2X0_CACHE_ID_RTL_MASK 0x3f
+#define L2X0_CACHE_ID_RTL_R3P2 0x8
+
#endif