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authorHarinarayan Bhatta <harinarayan@ti.com>2016-11-29 16:33:22 -0600
committerTom Rini <trini@konsulko.com>2016-12-03 13:21:20 -0500
commit4c158b9a7d05973e6924835726a2358b383d622f (patch)
tree2e41f4963f656d3f350016a33c2fb7526576eefc /arch/arm/include
parent7e719ee7d8eb61f459a38f69a825823603879258 (diff)
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arm: omap5: Add function to make an SMC call on cpu1
On DRA7xx platform, CPU Core 1 is not used in u-boot. However, in some cases it is need to make secure API calls from Core 1. This patch adds an assembly function to make a secure (SMC) call from CPU Core #1. Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/omap_common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 605c549..290a190 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -632,6 +632,7 @@ void omap_smc1(u32 service, u32 val);
* security (HS) device variants by doing a specially-formed smc entry.
*/
u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
void enable_edma3_clocks(void);
void disable_edma3_clocks(void);