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authorSimon Glass <sjg@chromium.org>2015-09-01 19:19:37 -0600
committerSimon Glass <sjg@chromium.org>2015-09-02 21:28:24 -0600
commit1b2fd5bf4eedfaf5af9d8fc219781fb521d12c7a (patch)
tree4c42fd099280d3d2fbbaf50f64cf11874b32e1d3 /arch/arm/include
parent3437469985df7c5403fa6e29b224e84c63bdbd52 (diff)
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rockchip: Add SPI driver
Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-rockchip/clock.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 2e5ba86..8a0376c 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -36,6 +36,26 @@ static inline int rk_pll_id(enum rk_clk_id clk_id)
}
/**
+ * clk_get_divisor() - Calculate the required clock divisior
+ *
+ * Given an input rate and a required output_rate, calculate the Rockchip
+ * divisor needed to achieve this.
+ *
+ * @input_rate: Input clock rate in Hz
+ * @output_rate: Output clock rate in Hz
+ * @return divisor register value to use
+ */
+static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
+{
+ uint clk_div;
+
+ clk_div = input_rate / output_rate;
+ clk_div = (clk_div + 1) & 0xfffe;
+
+ return clk_div;
+}
+
+/**
* rockchip_get_cru() - get a pointer to the clock/reset unit registers
*
* @return pointer to registers, or -ve error on error