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authorStefan Agner <stefan@agner.ch>2014-04-23 18:17:51 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-05-25 15:46:12 +0200
commit56d83d1c046c693b65ab09c0e960d922ec639c2b (patch)
tree87c48bc6742a97768be857d92f18976665d3feef /arch/arm/include
parent1277bac0d21bfa6952bdb14fcbf4134aa3018056 (diff)
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arm: vf610: add DDR_SEL_PAD_CONTR register
Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual. Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index c2f9761..0c28e1b 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -215,6 +215,7 @@
#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
+#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v) (((v) & 0x3) << 18)
#define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7)
#define DDRMC_CR158_TWR(v) ((v) & 0x3f)