ENGR00315894-58 RDC: Add an iMX platform driver for RDC-SEMA

The RDC driver provides interfaces for setting peripherals and masters
at BSP initialization, before using the peripherals driver. Another
interfaces for lock/unlock RDC semaphore and permission check.

The driver assumes boot CPU which runs u-boot is in Domain 0
(default setting on boot). Users should not set it to other domains.

The peripherals ID and masters ID may change on different chip, each
should provide definitions of the IDs and be included in "imx-rdc.h".

Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 964b2672bfbec14629f5767e59e73fd3bb185e3a)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Conflicts:
	arch/arm/imx-common/Makefile
	arch/arm/include/asm/arch-mx6/imx-regs.h

3 files changed, 71 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h b/arch/arm/include/asm/arch-mx6/imx-rdc.h
new file mode 100644
index 0000000..39e680e
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#ifndef __IMX_RDC_H__
+#define __IMX_RDC_H__
+
+#error "Please select cpu"
+
+#endif	/* __IMX_RDC_H__*/
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index e08253c..ea33a1a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -975,6 +975,30 @@ struct mxs_lcdif_regs {
 	u32	hw_lcdif_as_debug5;		/* 0x290 */
 };
 
+struct rdc_regs {
+	u32	vir;		/* Version information */
+	u32	reserved1[8];
+	u32	stat;		/* Status */
+	u32	intctrl;	/* Interrupt and Control */
+	u32	intstat;	/* Interrupt Status */
+	u32	reserved2[116];
+	u32	mda[32];		/* Master Domain Assignment */
+	u32	reserved3[96];
+	u32	pdap[104];		/* Peripheral Domain Access Permissions */
+	u32	reserved4[88];
+	struct {
+		u32 mrsa;		/* Memory Region Start Address */
+		u32 mrea;		/* Memory Region End Address */
+		u32 mrc;		/* Memory Region Control */
+		u32 mrvs;		/* Memory Region Violation Status */
+	} mem_region[55];
+};
+
+struct rdc_sema_regs {
+	u8	gate[64];	/* Gate */
+	u16	rstgt;		/* Reset Gate */
+};
+
 #define MXS_LCDIF_BASE LCDIF2_BASE_ADDR
 
 #define	LCDIF_CTRL_SFTRST					(1 << 31)
diff --git a/arch/arm/include/asm/imx-common/rdc-sema.h b/arch/arm/include/asm/imx-common/rdc-sema.h
new file mode 100644
index 0000000..01ffab2
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/rdc-sema.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:  GPL-2.0+
+ */
+
+#ifndef __RDC_SEMA_H__
+#define __RDC_SEMA_H__
+
+typedef u32 rdc_peri_cfg_t;
+typedef u32 rdc_ma_cfg_t;
+
+#define RDC_PERI_MASK 0xFF
+#define RDC_PERI_SHIFT 0
+
+#define RDC_DOMAIN_SHIFT_BASE   16
+#define RDC_DOMAIN_MASK 0xFF0000
+#define RDC_DOMAIN_SHIFT(x)   (RDC_DOMAIN_SHIFT_BASE + ((x << 1)))
+#define RDC_DOMAIN(x)	((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x)))
+
+#define RDC_MASTER_SHIFT   8
+#define RDC_MASTER_MASK 0xFF00
+#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | (domain_id << RDC_DOMAIN_SHIFT_BASE))
+
+int imx_rdc_check_permission(int per_id);
+int imx_rdc_sema_lock(int per_id);
+int imx_rdc_sema_unlock(int per_id);
+int imx_rdc_setup_peri(rdc_peri_cfg_t p);
+int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list,
+	unsigned count);
+int imx_rdc_setup_ma(rdc_ma_cfg_t p);
+int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list,
+	unsigned count);
+
+#endif	/* __RDC_SEMA_H__*/