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authorStefano Babic <sbabic@denx.de>2015-02-13 11:17:01 +0100
committerStefano Babic <sbabic@denx.de>2015-02-13 11:17:01 +0100
commite72d344386bf80738fab7a6bd37cb321f443093a (patch)
treed3e02055e6aa903ab80ef87c78d2f38e93981dcf /arch/arm/include
parent258c98f8d36ef35d7cb7604847ba73e64d702c2a (diff)
parentbd2a4888b123713adec271d6c8040ca9f609aa2f (diff)
downloadu-boot-imx-e72d344386bf80738fab7a6bd37cb321f443093a.zip
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Merge branch 'master' of git://git.denx.de/u-boot
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-armada-xp/config.h4
-rw-r--r--arch/arm/include/asm/arch-armada-xp/cpu.h16
-rw-r--r--arch/arm/include/asm/arch-at91/at91_common.h1
-rw-r--r--arch/arm/include/asm/arch-at91/at91_pmc.h9
-rw-r--r--arch/arm/include/asm/arch-at91/at91_rstc.h2
-rw-r--r--arch/arm/include/asm/arch-at91/at91cap9.h78
-rw-r--r--arch/arm/include/asm/arch-at91/at91cap9_matrix.h129
-rw-r--r--arch/arm/include/asm/arch-at91/at91sam9_matrix.h2
-rw-r--r--arch/arm/include/asm/arch-at91/atmel_usba_udc.h2
-rw-r--r--arch/arm/include/asm/arch-at91/hardware.h2
-rw-r--r--arch/arm/include/asm/arch-at91/sama5_matrix.h37
-rw-r--r--arch/arm/include/asm/arch-at91/sama5_sfr.h38
-rw-r--r--arch/arm/include/asm/arch-at91/sama5d4.h2
-rw-r--r--arch/arm/include/asm/arch-exynos/pinmux.h3
-rw-r--r--arch/arm/include/asm/arch-ls102xa/config.h5
-rw-r--r--arch/arm/include/asm/arch-ls102xa/gpio.h (renamed from arch/arm/include/asm/arch-uniphier/gpio.h)11
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h4
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h43
-rw-r--r--arch/arm/include/asm/arch-omap3/mmc_host_def.h1
-rw-r--r--arch/arm/include/asm/arch-omap3/mux.h51
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h20
-rw-r--r--arch/arm/include/asm/arch-pantheon/gpio.h0
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7790.h6
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7791.h5
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7793.h5
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7794.h5
-rw-r--r--arch/arm/include/asm/arch-rmobile/rcar-base.h3
-rw-r--r--arch/arm/include/asm/arch-rmobile/sh_sdhi.h168
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock.h6
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h13
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun6i.h7
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun9i.h139
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu.h148
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu_sun4i.h154
-rw-r--r--arch/arm/include/asm/arch-sunxi/cpu_sun9i.h109
-rw-r--r--arch/arm/include/asm/arch-sunxi/display.h120
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram_sun4i.h2
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h9
-rw-r--r--arch/arm/include/asm/arch-sunxi/mmc.h8
-rw-r--r--arch/arm/include/asm/arch-sunxi/rsb.h4
-rw-r--r--arch/arm/include/asm/arch-sunxi/usbc.h2
-rw-r--r--arch/arm/include/asm/arch-tegra/tegra_mmc.h7
-rw-r--r--arch/arm/include/asm/arch-tegra20/display.h9
-rw-r--r--arch/arm/include/asm/arch-uniphier/boot-device.h2
-rw-r--r--arch/arm/include/asm/arch-uniphier/ddrphy-regs.h2
-rw-r--r--arch/arm/include/asm/arch-uniphier/sg-regs.h109
-rw-r--r--arch/arm/include/asm/arch-zynq/gpio.h15
-rw-r--r--arch/arm/include/asm/arch-zynq/hardware.h5
-rw-r--r--arch/arm/include/asm/arch-zynq/sys_proto.h2
-rw-r--r--arch/arm/include/asm/u-boot-arm.h1
51 files changed, 1089 insertions, 437 deletions
diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/include/asm/arch-armada-xp/config.h
index 00ee775..f9fd424 100644
--- a/arch/arm/include/asm/arch-armada-xp/config.h
+++ b/arch/arm/include/asm/arch-armada-xp/config.h
@@ -31,7 +31,11 @@
#endif /* CONFIG_SYS_KWD_CONFIG */
/* Add target to build it automatically upon "make" */
+#ifdef CONFIG_SPL
+#define CONFIG_BUILD_TARGET "u-boot-spl.kwb"
+#else
#define CONFIG_BUILD_TARGET "u-boot.kwb"
+#endif
/* end of 16M scrubbed by training in bootrom */
#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000
diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h
index 6b60c21..4f5ff96 100644
--- a/arch/arm/include/asm/arch-armada-xp/cpu.h
+++ b/arch/arm/include/asm/arch-armada-xp/cpu.h
@@ -96,6 +96,9 @@ struct kwgpio_registers {
u32 irq_level;
};
+/* Needed for dynamic (board-specific) mbus configuration */
+extern struct mvebu_mbus_state mbus_state;
+
/*
* functions
*/
@@ -103,5 +106,18 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank);
unsigned int mvebu_sdram_bs(enum memory_bank bank);
void mvebu_sdram_size_adjust(enum memory_bank bank);
int mvebu_mbus_probe(struct mbus_win windows[], int count);
+
+/*
+ * Highspeed SERDES PHY config init, ported from bin_hdr
+ * to mainline U-Boot
+ */
+int serdes_phy_config(void);
+
+/*
+ * DDR3 init / training code ported from Marvell bin_hdr. Now
+ * available in mainline U-Boot in:
+ * drivers/ddr/mvebu/
+ */
+int ddr3_init(void);
#endif /* __ASSEMBLY__ */
#endif /* _ARMADA_XP_CPU_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
index 912e55c..efcd74e 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/include/asm/arch-at91/at91_common.h
@@ -33,5 +33,6 @@ void at91_mck_init(u32 mckr);
void at91_spl_board_init(void);
void at91_disable_wdt(void);
void matrix_init(void);
+void redirect_int_from_saic_to_aic(void);
#endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 53b5b2e..65691ab 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -157,10 +157,8 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
-#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@@ -175,7 +173,7 @@ typedef struct at91_pmc {
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
-#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
+#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
@@ -210,7 +208,7 @@ typedef struct at91_pmc {
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
-#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
+#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
@@ -230,8 +228,7 @@ typedef struct at91_pmc {
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
-#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
-#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h
index a942342..e4eb3da 100644
--- a/arch/arm/include/asm/arch-at91/at91_rstc.h
+++ b/arch/arm/include/asm/arch-at91/at91_rstc.h
@@ -13,6 +13,8 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
+/* Reset Controller Status Register */
+#define AT91_ASM_RSTC_SR (ATMEL_BASE_RSTC + 0x04)
#define AT91_ASM_RSTC_MR (ATMEL_BASE_RSTC + 0x08)
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h
deleted file mode 100644
index 63870bc..0000000
--- a/arch/arm/include/asm/arch-at91/at91cap9.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9.h]
- *
- * Copyright (C) 2007 Stelian Pop <stelian@popies.net>
- * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2007 Atmel Corporation.
- *
- * Common definitions.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91CAP9_H
-#define AT91CAP9_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
-#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
-#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
-#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
-#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
-#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
-#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
-#define AT91CAP9_ID_US0 8 /* USART 0 */
-#define AT91CAP9_ID_US1 9 /* USART 1 */
-#define AT91CAP9_ID_US2 10 /* USART 2 */
-#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
-#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
-#define AT91CAP9_ID_CAN 13 /* CAN */
-#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
-#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
-#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
-#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
-#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
-#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
-#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
-#define AT91CAP9_ID_EMAC 22 /* Ethernet */
-#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
-#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
-#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
-#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
-#define AT91CAP9_ID_DMA 27 /* DMA Controller */
-#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
-#define AT91CAP9_ID_UHP 29 /* USB Host Port */
-#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
-#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
-
-#define AT91_PIO_BASE 0xfffff200
-#define AT91_PMC_BASE 0xfffffc00
-#define AT91_RSTC_BASE 0xfffffd00
-#define AT91_PIT_BASE 0xfffffd30
-
-/*
- * Internal Memory.
- */
-#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
-#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
-
-#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
-#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
-
-#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
-#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
-#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
-
-#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
-
-/*
- * Cpu Name
- */
-#define CONFIG_SYS_AT91_CPU_NAME "AT91CAP9"
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h b/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
deleted file mode 100644
index 009a19d..0000000
--- a/arch/arm/include/asm/arch-at91/at91cap9_matrix.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/at91cap9_matrix.h]
- *
- * Copyright (C) 2007 Stelian Pop <stelian@popies.net>
- * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
- * Copyright (C) 2006 Atmel Corporation.
- *
- * Memory Controllers (MATRIX, EBI) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B (Preliminary).
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91CAP9_MATRIX_H
-#define AT91CAP9_MATRIX_H
-
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
-#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
-#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
-#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
-#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
-
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-#define AT91_MATRIX_RCB11 (1 << 11)
-
-#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
-#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
-
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
-#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-
-#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
-#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
-#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
-
-#endif
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
index 1b59cc6..d0bf0c2 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_matrix.h
@@ -15,8 +15,6 @@
#include <asm/arch/at91sam9263_matrix.h>
#elif defined(CONFIG_AT91SAM9RL)
#include <asm/arch/at91sam9rl_matrix.h>
-#elif defined(CONFIG_AT91CAP9)
-#include <asm/arch/at91cap9_matrix.h>
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
#include <asm/arch/at91sam9g45_matrix.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
diff --git a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
index 6f540d2..38b5012 100644
--- a/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
+++ b/arch/arm/include/asm/arch-at91/atmel_usba_udc.h
@@ -31,7 +31,7 @@ static struct usba_ep_data usba_udc_ep[] = {
EP("ep5", 5, 1024, 3, 1, 1),
EP("ep6", 6, 1024, 3, 1, 1),
};
-#elif defined(CONFIG_SAMA5D3)
+#elif defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
static struct usba_ep_data usba_udc_ep[] = {
EP("ep0", 0, 64, 1, 0, 0),
EP("ep1", 1, 1024, 3, 1, 0),
diff --git a/arch/arm/include/asm/arch-at91/hardware.h b/arch/arm/include/asm/arch-at91/hardware.h
index bf0a1bd..ff6b71b 100644
--- a/arch/arm/include/asm/arch-at91/hardware.h
+++ b/arch/arm/include/asm/arch-at91/hardware.h
@@ -23,8 +23,6 @@
# include <asm/arch/at91sam9g45.h>
#elif defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5)
# include <asm/arch/at91sam9x5.h>
-#elif defined(CONFIG_AT91CAP9)
-# include <asm/arch/at91cap9.h>
#elif defined(CONFIG_SAMA5D3)
# include <asm/arch/sama5d3.h>
#elif defined(CONFIG_SAMA5D4)
diff --git a/arch/arm/include/asm/arch-at91/sama5_matrix.h b/arch/arm/include/asm/arch-at91/sama5_matrix.h
new file mode 100644
index 0000000..e324766
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5_matrix.h
@@ -0,0 +1,37 @@
+/*
+ * Bus Matrix header file for the SAMA5 family
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5_MATRIX_H
+#define __SAMA5_MATRIX_H
+
+struct atmel_matrix {
+ u32 mcfg[16]; /* 0x00 ~ 0x3c: Master Configuration Register */
+ u32 scfg[16]; /* 0x40 ~ 0x7c: Slave Configuration Register */
+ u32 pras[16][2];/* 0x80 ~ 0xfc: Priority Register A/B */
+ u32 res1[20]; /* 0x100 ~ 0x14c */
+ u32 meier; /* 0x150: Master Error Interrupt Enable Register */
+ u32 meidr; /* 0x154: Master Error Interrupt Disable Register */
+ u32 meimr; /* 0x158: Master Error Interrupt Mask Register */
+ u32 mesr; /* 0x15c: Master Error Status Register */
+ u32 mear[16]; /* 0x160 ~ 0x19c: Master Error Address Register */
+ u32 res2[17]; /* 0x1A0 ~ 0x1E0 */
+ u32 wpmr; /* 0x1E4: Write Protection Mode Register */
+ u32 wpsr; /* 0x1E8: Write Protection Status Register */
+ u32 res3[5]; /* 0x1EC ~ 0x1FC */
+ u32 ssr[16]; /* 0x200 ~ 0x23c: Security Slave Register */
+ u32 sassr[16]; /* 0x240 ~ 0x27c: Security Areas Split Slave Register */
+ u32 srtsr[16]; /* 0x280 ~ 0x2bc: Security Region Top Slave */
+ u32 spselr[3]; /* 0x2c0 ~ 0x2c8: Security Peripheral Select Register */
+};
+
+/* Bit field in WPMR */
+#define ATMEL_MATRIX_WPMR_WPKEY 0x4D415400
+#define ATMEL_MATRIX_WPMR_WPEN 0x00000001
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5_sfr.h b/arch/arm/include/asm/arch-at91/sama5_sfr.h
new file mode 100644
index 0000000..3081d37
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/sama5_sfr.h
@@ -0,0 +1,38 @@
+/*
+ * Special Function Register (SFR)
+ *
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SAMA5_SFR_H
+#define __SAMA5_SFR_H
+
+struct atmel_sfr {
+ u32 reserved1; /* 0x00 */
+ u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ u32 reserved2; /* 0x08 */
+ u32 reserved3; /* 0x0c */
+ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
+ u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
+ u32 reserved4[4]; /* 0x18 ~ 0x24 */
+ u32 secure; /* 0x28: Security Configuration Register */
+ u32 reserved5[5]; /* 0x2c ~ 0x3c */
+ u32 ebicfg; /* 0x40: EBI Configuration Register */
+ u32 reserved6[2]; /* 0x44 ~ 0x48 */
+ u32 sn0; /* 0x4c */
+ u32 sn1; /* 0x50 */
+ u32 aicredir; /* 0x54 */
+};
+
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
+#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
+
+/* Bit field in AICREDIR */
+#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
+#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/sama5d4.h b/arch/arm/include/asm/arch-at91/sama5d4.h
index d851568..f30cb5f 100644
--- a/arch/arm/include/asm/arch-at91/sama5d4.h
+++ b/arch/arm/include/asm/arch-at91/sama5d4.h
@@ -126,6 +126,8 @@
#define ATMEL_BASE_ADC 0xfc034000
#define ATMEL_BASE_TWI3 0xfc038000
+#define ATMEL_BASE_MATRIX1 0xfc054000
+
#define ATMEL_BASE_SMC 0xfc05c000
#define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
#define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h
index 0b91ef6..d0ae757 100644
--- a/arch/arm/include/asm/arch-exynos/pinmux.h
+++ b/arch/arm/include/asm/arch-exynos/pinmux.h
@@ -23,6 +23,9 @@ enum {
/* Flags for SROM controller */
PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+
+ /* Flags for I2C */
+ PINMUX_FLAG_HS_MODE = 1 << 1, /* I2C High Speed Mode */
};
/**
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 5e934da..7915518 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -97,8 +97,13 @@
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#define CONFIG_SYS_FSL_ERRATUM_A008378
#else
#error SoC not defined
#endif
+#define FSL_IFC_COMPAT "fsl,ifc"
+#define FSL_QSPI_COMPAT "fsl,ls1-qspi"
+#define FSL_DSPI_COMPAT "fsl,vf610-dspi"
+
#endif /* _ASM_ARMV7_LS102XA_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-uniphier/gpio.h b/arch/arm/include/asm/arch-ls102xa/gpio.h
index 1fc4e19..b704436 100644
--- a/arch/arm/include/asm/arch-uniphier/gpio.h
+++ b/arch/arm/include/asm/arch-ls102xa/gpio.h
@@ -1,6 +1,15 @@
/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*
* Dummy header file to enable CONFIG_OF_CONTROL.
* If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
* It includes <asm/arch/gpio.h> via <asm/gpio.h>, so those SoCs that enable
- * OF_CONTROL must have arch/gpio.h even if GPIO is not supported.
+ * OF_CONTROL must have arch/gpio.h.
*/
+
+#ifndef __ASM_ARCH_LS102XA_GPIO_H_
+#define __ASM_ARCH_LS102XA_GPIO_H_
+
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 697d4ca..f70d568 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -105,6 +105,8 @@ struct ccsr_gur {
#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
+#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
+#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
#define SCFG_PIXCLKCR_PXCKEN 0x80000000
#define SCFG_QSPI_CLKSEL 0xc0100000
@@ -456,6 +458,8 @@ struct ccsr_ddr {
#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
#define CCI400_CTRLORD_EN_BARRIER 0
#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
+#define CCI400_SNOOP_REQ_EN 0x00000001
/* CCI-400 registers */
struct ccsr_cci400 {
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index 0b78c1c..3ce270c 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -249,6 +249,49 @@ enum {
#define MICRON_RASWIDTH_200 14
#define MICRON_V_MCFG_200(size) MCFG((size), MICRON_RASWIDTH_200)
+/* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
+#define SAMSUNG_TDAL_165 5
+#define SAMSUNG_TDPL_165 2
+#define SAMSUNG_TRRD_165 2
+#define SAMSUNG_TRCD_165 3
+#define SAMSUNG_TRP_165 3
+#define SAMSUNG_TRAS_165 7
+#define SAMSUNG_TRC_165 10
+#define SAMSUNG_TRFC_165 12
+
+#define SAMSUNG_V_ACTIMA_165 \
+ ACTIM_CTRLA(SAMSUNG_TRFC_165, SAMSUNG_TRC_165, \
+ SAMSUNG_TRAS_165, SAMSUNG_TRP_165, \
+ SAMSUNG_TRCD_165, SAMSUNG_TRRD_165, \
+ SAMSUNG_TDPL_165, SAMSUNG_TDAL_165)
+
+#define SAMSUNG_TWTR_165 1
+#define SAMSUNG_TCKE_165 2
+#define SAMSUNG_XSR_165 20
+#define SAMSUNG_TXP_165 5
+
+#define SAMSUNG_V_ACTIMB_165 \
+ ACTIM_CTRLB(SAMSUNG_TWTR_165, SAMSUNG_TCKE_165, \
+ SAMSUNG_TXP_165, SAMSUNG_XSR_165)
+
+#define SAMSUNG_RASWIDTH_165 14
+#define SAMSUNG_V_MCFG_165(size) \
+ V_MCFG_RASWIDTH(SAMSUNG_RASWIDTH_165) | V_MCFG_CASWIDTH_10B | \
+ V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(size) | \
+ V_MCFG_BANKALLOCATION_RBC | V_MCFG_RAMTYPE_DDR
+
+/* TODO: find which register these were taken from */
+
+#define SAMSUNG_BL_165 0x2
+#define SAMSUNG_SIL_165 0x0
+#define SAMSUNG_CASL_165 0x3
+#define SAMSUNG_WBST_165 0x0
+#define SAMSUNG_V_MR_165 ((SAMSUNG_WBST_165 << 9) | \
+ (SAMSUNG_CASL_165 << 4) | (SAMSUNG_SIL_165 << 3) | \
+ (SAMSUNG_BL_165))
+
+#define SAMSUNG_SHARING 0x00003700
+
/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
/* 15/6 + 18/6 = 5.5 -> 6 */
diff --git a/arch/arm/include/asm/arch-omap3/mmc_host_def.h b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index 0ba621a..9f2896c 100644
--- a/arch/arm/include/asm/arch-omap3/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
@@ -51,6 +51,7 @@ typedef struct t2 {
#define PBIASLITEPWRDNZ0 (1 << 1)
#define PBIASSPEEDCTRL0 (1 << 2)
#define PBIASLITEPWRDNZ1 (1 << 9)
+#define PBIASLITEVMODE0 (1 << 0)
#define CTLPROGIO1SPEEDCTRL (1 << 20)
diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index eba4a5c..3277b40 100644
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -15,6 +15,12 @@
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
+ * SB_LOW - Standby mode configuration: Output low-level
+ * SB_HI - Standby mode configuration: Output high-level
+ * SB_HIZ - Standby mode configuration: Output hi-impedence
+ * SB_PD - Standby mode pull-down enabled
+ * SB_PU - Standby mode pull-up enabled
+ * WKEN - Wakeup input enabled
* M0 - Mode 0
*/
@@ -26,6 +32,13 @@
#define EN (1 << 3)
#define DIS (0 << 3)
+#define SB_LOW (1 << 9)
+#define SB_HI (5 << 9)
+#define SB_HIZ (2 << 9)
+#define SB_PD (1 << 12)
+#define SB_PU (3 << 12)
+#define WKEN (1 << 14)
+
#define M0 0
#define M1 1
#define M2 2
@@ -36,8 +49,8 @@
#define M7 7
/*
- * To get the actual address the offset has to added
- * with OMAP34XX_CTRL_BASE to get the actual address
+ * To get the actual address the offset has to be added
+ * to OMAP34XX_CTRL_BASE
*/
/*SDRC*/
@@ -78,6 +91,33 @@
#define CONTROL_PADCONF_SDRC_DQS1 0x0074
#define CONTROL_PADCONF_SDRC_DQS2 0x0076
#define CONTROL_PADCONF_SDRC_DQS3 0x0078
+#define CONTROL_PADCONF_SDRC_BA0 0x05A0
+#define CONTROL_PADCONF_SDRC_BA1 0x05A2
+#define CONTROL_PADCONF_SDRC_A0 0x05A4
+#define CONTROL_PADCONF_SDRC_A1 0x05A6
+#define CONTROL_PADCONF_SDRC_A2 0x05A8
+#define CONTROL_PADCONF_SDRC_A3 0x05AA
+#define CONTROL_PADCONF_SDRC_A4 0x05AC
+#define CONTROL_PADCONF_SDRC_A5 0x05AE
+#define CONTROL_PADCONF_SDRC_A6 0x05B0
+#define CONTROL_PADCONF_SDRC_A7 0x05B2
+#define CONTROL_PADCONF_SDRC_A8 0x05B4
+#define CONTROL_PADCONF_SDRC_A9 0x05B6
+#define CONTROL_PADCONF_SDRC_A10 0x05B8
+#define CONTROL_PADCONF_SDRC_A11 0x05BA
+#define CONTROL_PADCONF_SDRC_A12 0x05BC
+#define CONTROL_PADCONF_SDRC_A13 0x05BE
+#define CONTROL_PADCONF_SDRC_A14 0x05C0
+#define CONTROL_PADCONF_SDRC_NCS0 0x05C2
+#define CONTROL_PADCONF_SDRC_NCS1 0x05C4
+#define CONTROL_PADCONF_SDRC_NCLK 0x05C6
+#define CONTROL_PADCONF_SDRC_NRAS 0x05C8
+#define CONTROL_PADCONF_SDRC_NCAS 0x05CA
+#define CONTROL_PADCONF_SDRC_NWE 0x05CC
+#define CONTROL_PADCONF_SDRC_DM0 0x05CE
+#define CONTROL_PADCONF_SDRC_DM1 0x05D0
+#define CONTROL_PADCONF_SDRC_DM2 0x05D2
+#define CONTROL_PADCONF_SDRC_DM3 0x05D4
/*GPMC*/
#define CONTROL_PADCONF_GPMC_A1 0x007A
#define CONTROL_PADCONF_GPMC_A2 0x007C
@@ -89,6 +129,7 @@
#define CONTROL_PADCONF_GPMC_A8 0x0088
#define CONTROL_PADCONF_GPMC_A9 0x008A
#define CONTROL_PADCONF_GPMC_A10 0x008C
+#define CONTROL_PADCONF_GPMC_A11 0x0264
#define CONTROL_PADCONF_GPMC_D0 0x008E
#define CONTROL_PADCONF_GPMC_D1 0x0090
#define CONTROL_PADCONF_GPMC_D2 0x0092
@@ -323,6 +364,8 @@
#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6
#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8
#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA
+#define CONTROL_PADCONF_JTAG_RTCK 0x0A4E
+#define CONTROL_PADCONF_JTAG_TDO 0x0A50
/*Die to Die */
#define CONTROL_PADCONF_D2D_MCAD0 0x01E4
#define CONTROL_PADCONF_D2D_MCAD1 0x01E6
@@ -433,6 +476,10 @@
#define CONTROL_PADCONF_SYS_BOOT8 0x0226
/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO112 0x0134
+#define CONTROL_PADCONF_GPIO113 0x0136
+#define CONTROL_PADCONF_GPIO114 0x0138
+#define CONTROL_PADCONF_GPIO115 0x013A
#define CONTROL_PADCONF_GPIO127 0x0A54
#define CONTROL_PADCONF_GPIO126 0x0A56
#define CONTROL_PADCONF_GPIO128 0x0A58
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 34bd8c5..bcf92fb 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -23,6 +23,7 @@ struct emu_hal_params {
/* Board SDRC timing values */
struct board_sdrc_timings {
+ u32 sharing;
u32 mcfg;
u32 ctrla;
u32 ctrlb;
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 0dc584b..f8e5630 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -236,13 +236,20 @@
#define VDD_MPU_ES2_LOW 880
#define VDD_MM_ES2_LOW 880
-/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
-#define VDD_MPU_DRA752 1090
+/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA752 1100
#define VDD_EVE_DRA752 1060
#define VDD_GPU_DRA752 1060
-#define VDD_CORE_DRA752 1030
+#define VDD_CORE_DRA752 1060
#define VDD_IVA_DRA752 1060
+/* DRA72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA72x 1100
+#define VDD_EVE_DRA72x 1060
+#define VDD_GPU_DRA72x 1060
+#define VDD_CORE_DRA72x 1060
+#define VDD_IVA_DRA72x 1060
+
/* Efuse register offsets for DRA7xx platform */
#define DRA752_EFUSE_BASE 0x4A002000
#define DRA752_EFUSE_REGBITS 16
@@ -284,6 +291,13 @@
#define TPS659038_REG_ADDR_SMPS7 0x33
#define TPS659038_REG_ADDR_SMPS8 0x37
+/* TPS65917 */
+#define TPS65917_I2C_SLAVE_ADDR 0x58
+#define TPS65917_REG_ADDR_SMPS1 0x23
+#define TPS65917_REG_ADDR_SMPS2 0x27
+#define TPS65917_REG_ADDR_SMPS3 0x2F
+
+
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
#define TPS62361_REG_ADDR_SET0 0x0
diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/gpio.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index 132d58c..748b802 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -28,6 +28,12 @@
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x00000000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+
#define R8A7790_CUT_ES2X 2
#define IS_R8A7790_ES2() \
(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index d2cbcd7..1d06b65 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -17,6 +17,11 @@
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/include/asm/arch-rmobile/r8a7793.h
index 1abdeb7..3efc62a 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7793.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7793.h
@@ -18,6 +18,11 @@
/* SH-I2C */
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
#define DBSC3_1_QOS_R0_BASE 0xE67A1000
#define DBSC3_1_QOS_R1_BASE 0xE67A1100
#define DBSC3_1_QOS_R2_BASE 0xE67A1200
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/include/asm/arch-rmobile/r8a7794.h
index d7c9004..6d11fa4 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7794.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7794.h
@@ -27,4 +27,9 @@
#define MSTP10_BITS 0xFFFEFFE0
#define MSTP11_BITS 0x000001C0
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
#endif /* __ASM_ARCH_R8A7794_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 23c4bba..d594cd7 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -82,6 +82,9 @@
#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
+
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
#define S3C_MEDIA_BASE 0xE6784B00
diff --git a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h
new file mode 100644
index 0000000..057bf3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/sh_sdhi.h
@@ -0,0 +1,168 @@
+/*
+ * drivers/mmc/sh-sdhi.h
+ *
+ * SD/MMC driver for Reneas rmobile ARM SoCs
+ *
+ * Copyright (C) 2013-2014 Renesas Electronics Corporation
+ * Copyright (C) 2008-2009 Renesas Solutions Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef _SH_SDHI_H
+#define _SH_SDHI_H
+
+#define SDHI_CMD (0x0000 >> 1)
+#define SDHI_PORTSEL (0x0004 >> 1)
+#define SDHI_ARG0 (0x0008 >> 1)
+#define SDHI_ARG1 (0x000C >> 1)
+#define SDHI_STOP (0x0010 >> 1)
+#define SDHI_SECCNT (0x0014 >> 1)
+#define SDHI_RSP00 (0x0018 >> 1)
+#define SDHI_RSP01 (0x001C >> 1)
+#define SDHI_RSP02 (0x0020 >> 1)
+#define SDHI_RSP03 (0x0024 >> 1)
+#define SDHI_RSP04 (0x0028 >> 1)
+#define SDHI_RSP05 (0x002C >> 1)
+#define SDHI_RSP06 (0x0030 >> 1)
+#define SDHI_RSP07 (0x0034 >> 1)
+#define SDHI_INFO1 (0x0038 >> 1)
+#define SDHI_INFO2 (0x003C >> 1)
+#define SDHI_INFO1_MASK (0x0040 >> 1)
+#define SDHI_INFO2_MASK (0x0044 >> 1)
+#define SDHI_CLK_CTRL (0x0048 >> 1)
+#define SDHI_SIZE (0x004C >> 1)
+#define SDHI_OPTION (0x0050 >> 1)
+#define SDHI_ERR_STS1 (0x0058 >> 1)
+#define SDHI_ERR_STS2 (0x005C >> 1)
+#define SDHI_BUF0 (0x0060 >> 1)
+#define SDHI_SDIO_MODE (0x0068 >> 1)
+#define SDHI_SDIO_INFO1 (0x006C >> 1)
+#define SDHI_SDIO_INFO1_MASK (0x0070 >> 1)
+#define SDHI_CC_EXT_MODE (0x01B0 >> 1)
+#define SDHI_SOFT_RST (0x01C0 >> 1)
+#define SDHI_VERSION (0x01C4 >> 1)
+#define SDHI_HOST_MODE (0x01C8 >> 1)
+#define SDHI_SDIF_MODE (0x01CC >> 1)
+#define SDHI_EXT_SWAP (0x01E0 >> 1)
+#define SDHI_SD_DMACR (0x0324 >> 1)
+
+/* SDHI CMD VALUE */
+#define CMD_MASK 0x0000ffff
+#define SDHI_APP 0x0040
+#define SDHI_SD_APP_SEND_SCR 0x0073
+#define SDHI_SD_SWITCH 0x1C06
+
+/* SDHI_PORTSEL */
+#define USE_1PORT (1 << 8) /* 1 port */
+
+/* SDHI_ARG */
+#define ARG0_MASK 0x0000ffff
+#define ARG1_MASK 0x0000ffff
+
+/* SDHI_STOP */
+#define STOP_SEC_ENABLE (1 << 8)
+
+/* SDHI_INFO1 */
+#define INFO1_RESP_END (1 << 0)
+#define INFO1_ACCESS_END (1 << 2)
+#define INFO1_CARD_RE (1 << 3)
+#define INFO1_CARD_IN (1 << 4)
+#define INFO1_ISD0CD (1 << 5)
+#define INFO1_WRITE_PRO (1 << 7)
+#define INFO1_DATA3_CARD_RE (1 << 8)
+#define INFO1_DATA3_CARD_IN (1 << 9)
+#define INFO1_DATA3 (1 << 10)
+
+/* SDHI_INFO2 */
+#define INFO2_CMD_ERROR (1 << 0)
+#define INFO2_CRC_ERROR (1 << 1)
+#define INFO2_END_ERROR (1 << 2)
+#define INFO2_TIMEOUT (1 << 3)
+#define INFO2_BUF_ILL_WRITE (1 << 4)
+#define INFO2_BUF_ILL_READ (1 << 5)
+#define INFO2_RESP_TIMEOUT (1 << 6)
+#define INFO2_SDDAT0 (1 << 7)
+#define INFO2_BRE_ENABLE (1 << 8)
+#define INFO2_BWE_ENABLE (1 << 9)
+#define INFO2_CBUSY (1 << 14)
+#define INFO2_ILA (1 << 15)
+#define INFO2_ALL_ERR (0x807f)
+
+/* SDHI_INFO1_MASK */
+#define INFO1M_RESP_END (1 << 0)
+#define INFO1M_ACCESS_END (1 << 2)
+#define INFO1M_CARD_RE (1 << 3)
+#define INFO1M_CARD_IN (1 << 4)
+#define INFO1M_DATA3_CARD_RE (1 << 8)
+#define INFO1M_DATA3_CARD_IN (1 << 9)
+#define INFO1M_ALL (0xffff)
+#define INFO1M_SET (INFO1M_RESP_END | \
+ INFO1M_ACCESS_END | \
+ INFO1M_DATA3_CARD_RE | \
+ INFO1M_DATA3_CARD_IN)
+
+/* SDHI_INFO2_MASK */
+#define INFO2M_CMD_ERROR (1 << 0)
+#define INFO2M_CRC_ERROR (1 << 1)
+#define INFO2M_END_ERROR (1 << 2)
+#define INFO2M_TIMEOUT (1 << 3)
+#define INFO2M_BUF_ILL_WRITE (1 << 4)
+#define INFO2M_BUF_ILL_READ (1 << 5)
+#define INFO2M_RESP_TIMEOUT (1 << 6)
+#define INFO2M_BRE_ENABLE (1 << 8)
+#define INFO2M_BWE_ENABLE (1 << 9)
+#define INFO2M_ILA (1 << 15)
+#define INFO2M_ALL (0xffff)
+#define INFO2M_ALL_ERR (0x807f)
+
+/* SDHI_CLK_CTRL */
+#define CLK_ENABLE (1 << 8)
+
+/* SDHI_OPTION */
+#define OPT_BUS_WIDTH_1 (1 << 15) /* bus width = 1 bit */
+
+/* SDHI_ERR_STS1 */
+#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \
+ (1 << 8) | (1 << 5))
+#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \
+ (1 << 1) | (1 << 0))
+
+/* SDHI_ERR_STS2 */
+#define ERR_STS2_RES_TIMEOUT (1 << 0)
+#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1))
+#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \
+ (1 << 3) | (1 << 2) | (1 << 1) | \
+ (1 << 0))
+
+/* SDHI_SDIO_MODE */
+#define SDIO_MODE_ON (1 << 0)
+#define SDIO_MODE_OFF (0 << 0)
+
+/* SDHI_SDIO_INFO1 */
+#define SDIO_INFO1_IOIRQ (1 << 0)
+#define SDIO_INFO1_EXPUB52 (1 << 14)
+#define SDIO_INFO1_EXWT (1 << 15)
+
+/* SDHI_SDIO_INFO1_MASK */
+#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2))
+#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \
+ (1 << 1) | (1 << 0))
+
+/* SDHI_EXT_SWAP */
+#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */
+
+/* SDHI_SOFT_RST */
+#define SOFT_RST_ON (0 << 0)
+#define SOFT_RST_OFF (1 << 0)
+
+#define CLKDEV_SD_DATA 25000000 /* 25 MHz */
+#define CLKDEV_HS_DATA 50000000 /* 50 MHz */
+#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
+#define CLKDEV_INIT 400000 /* 100 - 400 KHz */
+
+/* For quirk */
+#define SH_SDHI_QUIRK_16BIT_BUF (1)
+int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
+
+#endif /* _SH_SDHI_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 505c363..3e5d999 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -17,6 +17,8 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
#include <asm/arch/clock_sun6i.h>
+#elif defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/clock_sun9i.h>
#else
#include <asm/arch/clock_sun4i.h>
#endif
@@ -24,10 +26,6 @@
#ifndef __ASSEMBLY__
int clock_init(void);
int clock_twi_onoff(int port, int state);
-void clock_set_pll1(unsigned int hz);
-void clock_set_pll3(unsigned int hz);
-unsigned int clock_get_pll5p(void);
-unsigned int clock_get_pll6(void);
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
void clock_init_uart(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 84a9a2b..d297ed0 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -186,6 +186,7 @@ struct sunxi_ccm_reg {
/* ahb clock gate bit offset (second register) */
#define AHB_GATE_OFFSET_GMAC 17
+#define AHB_GATE_OFFSET_DE_FE0 14
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
@@ -266,7 +267,10 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_PLL5 (0x2 << 24)
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */
+#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
@@ -301,6 +305,8 @@ struct sunxi_ccm_reg {
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
@@ -320,4 +326,11 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_RST (1 << 30)
#define CCM_DE_CTRL_GATE (1 << 31)
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll5p(void);
+unsigned int clock_get_pll6(void);
+#endif
+
#endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 4711260..8a80385 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -243,6 +243,8 @@ struct sunxi_ccm_reg {
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
@@ -320,6 +322,11 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+unsigned int clock_get_pll6(void);
+#endif
#endif /* _SUNXI_CLOCK_SUN6I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
new file mode 100644
index 0000000..c506b0a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -0,0 +1,139 @@
+/*
+ * sun9i clock register definitions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN9I_H
+#define _SUNXI_CLOCK_SUN9I_H
+
+struct sunxi_ccm_reg {
+ u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
+ u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
+ u32 pll3_audio_cfg; /* 0x08 audio pll configuration */
+ u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */
+ u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */
+ u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */
+ u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */
+ u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */
+ u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */
+ u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */
+ u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */
+ u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */
+ u8 reserved1[0x20]; /* 0x30 */
+ u32 cpu_clk_source; /* 0x50 cpu clk source configuration */
+ u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */
+ u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */
+ u32 gtbus_cfg; /* 0x5c gtbus clock configuration */
+ u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */
+ u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */
+ u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */
+ u8 reserved2[0x04]; /* 0x6c */
+ u32 apb0_cfg; /* 0x70 apb0 clock configuration */
+ u32 apb1_cfg; /* 0x74 apb1 clock configuration */
+ u32 cci400_cfg; /* 0x78 cci400 clock configuration */
+ u8 reserved3[0x04]; /* 0x7c */
+ u32 ats_cfg; /* 0x80 ats clock configuration */
+ u32 trace_cfg; /* 0x84 trace clock configuration */
+ u8 reserved4[0xf8]; /* 0x88 */
+ u32 clk_output_a; /* 0x180 clk_output_a */
+ u32 clk_output_b; /* 0x184 clk_output_a */
+ u8 reserved5[0x278]; /* 0x188 */
+
+ u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */
+ u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
+ u8 reserved6[0x08]; /* 0x408 */
+ u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */
+ u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */
+ u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */
+ u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */
+ u8 reserved7[0x08]; /* 0x420 */
+ u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
+ u32 ss_clk_cfg; /* 0x42c security system clock cfg */
+ u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
+ u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
+ u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
+ u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
+ u8 reserved8[0x50]; /* 0x440 */
+ u32 de_clk_cfg; /* 0x490 display engine clock configuration */
+ u8 reserved9[0x04]; /* 0x494 */
+ u32 mp_clk_cfg; /* 0x498 mp clock configuration */
+ u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */
+ u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */
+ u8 reserved10[0x1c]; /* 0x4a4 */
+ u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */
+ u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */
+ u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */
+ u32 fd_clk_cfg; /* 0x4cc FD module clock */
+ u32 ve_clk_cfg; /* 0x4d0 VE module clock */
+ u32 avs_clk_cfg; /* 0x4d4 AVS module clock */
+ u8 reserved11[0x18]; /* 0x4d8 */
+ u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */
+ u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */
+ u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */
+ u8 reserved12[0x10]; /* 0x4fc */
+ u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
+ u8 reserved13[0x70]; /* 0x510 */
+
+ u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
+ u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
+ u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
+ u8 reserved14[0x04]; /* 0x58c */
+ u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
+ u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
+ u8 reserved15[0x08]; /* 0x598 */
+ u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */
+ u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */
+ u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */
+ u8 reserved16[0x04]; /* 0x5ac */
+ u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */
+ u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */
+};
+
+/* pll4_periph0_cfg */
+#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */
+
+#define CCM_PLL4_CTRL_N_SHIFT 8
+#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT)
+#define CCM_PLL4_CTRL_P_SHIFT 16
+#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT)
+#define CCM_PLL4_CTRL_M_SHIFT 18
+#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT)
+
+/* sd#_clk_cfg fields */
+#define CCM_MMC_CTRL_M(x) ((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
+#define CCM_MMC_CTRL_N(x) ((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
+#define CCM_MMC_CTRL_OSCM24 (0 << 24)
+#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24)
+#define CCM_MMC_CTRL_ENABLE (1 << 31)
+
+/* ahb_gate0 fields */
+/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_MMC(x) 8
+
+/* apb1_gate fields */
+#define APB1_GATE_UART_SHIFT 16
+#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
+#define APB1_GATE_TWI_SHIFT 0
+#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
+
+/* ahb_reset0_cfg fields */
+/* On sun9i all sdc-s share their ahb reset, so ignore (x) */
+#define AHB_RESET_OFFSET_MMC(x) 8
+
+/* apb1_reset_cfg fields */
+#define APB1_RESET_UART_SHIFT 16
+#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT)
+#define APB1_RESET_TWI_SHIFT 0
+#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT)
+
+
+#ifndef __ASSEMBLY__
+unsigned int clock_get_pll4_periph0(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 82b3d46..73583ed 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -1,7 +1,5 @@
/*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -9,146 +7,10 @@
#ifndef _SUNXI_CPU_H
#define _SUNXI_CPU_H
-#define SUNXI_SRAM_A1_BASE 0x00000000
-#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
-
-#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
-#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
-#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
-#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
-#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
-
-#define SUNXI_SRAMC_BASE 0x01c00000
-#define SUNXI_DRAMC_BASE 0x01c01000
-#define SUNXI_DMA_BASE 0x01c02000
-#define SUNXI_NFC_BASE 0x01c03000
-#define SUNXI_TS_BASE 0x01c04000
-#define SUNXI_SPI0_BASE 0x01c05000
-#define SUNXI_SPI1_BASE 0x01c06000
-#define SUNXI_MS_BASE 0x01c07000
-#define SUNXI_TVD_BASE 0x01c08000
-#define SUNXI_CSI0_BASE 0x01c09000
-#define SUNXI_TVE0_BASE 0x01c0a000
-#define SUNXI_EMAC_BASE 0x01c0b000
-#define SUNXI_LCD0_BASE 0x01c0C000
-#define SUNXI_LCD1_BASE 0x01c0d000
-#define SUNXI_VE_BASE 0x01c0e000
-#define SUNXI_MMC0_BASE 0x01c0f000
-#define SUNXI_MMC1_BASE 0x01c10000
-#define SUNXI_MMC2_BASE 0x01c11000
-#define SUNXI_MMC3_BASE 0x01c12000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
-#define SUNXI_USB0_BASE 0x01c13000
-#define SUNXI_USB1_BASE 0x01c14000
-#endif
-#define SUNXI_SS_BASE 0x01c15000
-#define SUNXI_HDMI_BASE 0x01c16000
-#define SUNXI_SPI2_BASE 0x01c17000
-#define SUNXI_SATA_BASE 0x01c18000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
-#define SUNXI_PATA_BASE 0x01c19000
-#define SUNXI_ACE_BASE 0x01c1a000
-#define SUNXI_TVE1_BASE 0x01c1b000
-#define SUNXI_USB2_BASE 0x01c1c000
+#if defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/cpu_sun9i.h>
#else
-#define SUNXI_USB0_BASE 0x01c19000
-#define SUNXI_USB1_BASE 0x01c1a000
-#define SUNXI_USB2_BASE 0x01c1b000
+#include <asm/arch/cpu_sun4i.h>
#endif
-#define SUNXI_CSI1_BASE 0x01c1d000
-#define SUNXI_TZASC_BASE 0x01c1e000
-#define SUNXI_SPI3_BASE 0x01c1f000
-
-#define SUNXI_CCM_BASE 0x01c20000
-#define SUNXI_INTC_BASE 0x01c20400
-#define SUNXI_PIO_BASE 0x01c20800
-#define SUNXI_TIMER_BASE 0x01c20c00
-#define SUNXI_SPDIF_BASE 0x01c21000
-#define SUNXI_AC97_BASE 0x01c21400
-#define SUNXI_IR0_BASE 0x01c21800
-#define SUNXI_IR1_BASE 0x01c21c00
-
-#define SUNXI_IIS_BASE 0x01c22400
-#define SUNXI_LRADC_BASE 0x01c22800
-#define SUNXI_AD_DA_BASE 0x01c22c00
-#define SUNXI_KEYPAD_BASE 0x01c23000
-#define SUNXI_TZPC_BASE 0x01c23400
-#define SUNXI_SID_BASE 0x01c23800
-#define SUNXI_SJTAG_BASE 0x01c23c00
-
-#define SUNXI_TP_BASE 0x01c25000
-#define SUNXI_PMU_BASE 0x01c25400
-#define SUN7I_CPUCFG_BASE 0x01c25c00
-
-#define SUNXI_UART0_BASE 0x01c28000
-#define SUNXI_UART1_BASE 0x01c28400
-#define SUNXI_UART2_BASE 0x01c28800
-#define SUNXI_UART3_BASE 0x01c28c00
-#define SUNXI_UART4_BASE 0x01c29000
-#define SUNXI_UART5_BASE 0x01c29400
-#define SUNXI_UART6_BASE 0x01c29800
-#define SUNXI_UART7_BASE 0x01c29c00
-#define SUNXI_PS2_0_BASE 0x01c2a000
-#define SUNXI_PS2_1_BASE 0x01c2a400
-
-#define SUNXI_TWI0_BASE 0x01c2ac00
-#define SUNXI_TWI1_BASE 0x01c2b000
-#define SUNXI_TWI2_BASE 0x01c2b400
-
-#define SUNXI_CAN_BASE 0x01c2bc00
-
-#define SUNXI_SCR_BASE 0x01c2c400
-
-#ifndef CONFIG_MACH_SUN6I
-#define SUNXI_GPS_BASE 0x01c30000
-#define SUNXI_MALI400_BASE 0x01c40000
-#define SUNXI_GMAC_BASE 0x01c50000
-#else
-#define SUNXI_GMAC_BASE 0x01c30000
-#endif
-
-#define SUNXI_DRAM_COM_BASE 0x01c62000
-#define SUNXI_DRAM_CTL0_BASE 0x01c63000
-#define SUNXI_DRAM_CTL1_BASE 0x01c64000
-#define SUNXI_DRAM_PHY0_BASE 0x01c65000
-#define SUNXI_DRAM_PHY1_BASE 0x01c66000
-
-/* module sram */
-#define SUNXI_SRAM_C_BASE 0x01d00000
-
-#define SUNXI_DE_FE0_BASE 0x01e00000
-#define SUNXI_DE_FE1_BASE 0x01e20000
-#define SUNXI_DE_BE0_BASE 0x01e60000
-#define SUNXI_DE_BE1_BASE 0x01e40000
-#define SUNXI_MP_BASE 0x01e80000
-#define SUNXI_AVG_BASE 0x01ea0000
-
-#define SUNXI_RTC_BASE 0x01f00000
-#define SUNXI_PRCM_BASE 0x01f01400
-#define SUN6I_CPUCFG_BASE 0x01f01c00
-#define SUNXI_R_UART_BASE 0x01f02800
-#define SUNXI_R_PIO_BASE 0x01f02c00
-#define SUN6I_P2WI_BASE 0x01f03400
-#define SUNXI_RSB_BASE 0x01f03400
-
-/* CoreSight Debug Module */
-#define SUNXI_CSDM_BASE 0x3f500000
-
-#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
-
-#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
-
-#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
-
-/* SS bonding ids used for cpu identification */
-#define SUNXI_SS_BOND_ID_A31 4
-#define SUNXI_SS_BOND_ID_A31S 5
-
-#ifndef __ASSEMBLY__
-void sunxi_board_init(void);
-void sunxi_reset(void);
-int sunxi_get_ss_bonding_id(void);
-int sunxi_get_sid(unsigned int *sid);
-#endif /* __ASSEMBLY__ */
-#endif /* _CPU_H */
+#endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
new file mode 100644
index 0000000..dae6069
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN4I_H
+#define _SUNXI_CPU_SUN4I_H
+
+#define SUNXI_SRAM_A1_BASE 0x00000000
+#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
+
+#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
+#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
+#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
+#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
+#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
+
+#define SUNXI_SRAMC_BASE 0x01c00000
+#define SUNXI_DRAMC_BASE 0x01c01000
+#define SUNXI_DMA_BASE 0x01c02000
+#define SUNXI_NFC_BASE 0x01c03000
+#define SUNXI_TS_BASE 0x01c04000
+#define SUNXI_SPI0_BASE 0x01c05000
+#define SUNXI_SPI1_BASE 0x01c06000
+#define SUNXI_MS_BASE 0x01c07000
+#define SUNXI_TVD_BASE 0x01c08000
+#define SUNXI_CSI0_BASE 0x01c09000
+#define SUNXI_TVE0_BASE 0x01c0a000
+#define SUNXI_EMAC_BASE 0x01c0b000
+#define SUNXI_LCD0_BASE 0x01c0C000
+#define SUNXI_LCD1_BASE 0x01c0d000
+#define SUNXI_VE_BASE 0x01c0e000
+#define SUNXI_MMC0_BASE 0x01c0f000
+#define SUNXI_MMC1_BASE 0x01c10000
+#define SUNXI_MMC2_BASE 0x01c11000
+#define SUNXI_MMC3_BASE 0x01c12000
+#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#define SUNXI_USB0_BASE 0x01c13000
+#define SUNXI_USB1_BASE 0x01c14000
+#endif
+#define SUNXI_SS_BASE 0x01c15000
+#define SUNXI_HDMI_BASE 0x01c16000
+#define SUNXI_SPI2_BASE 0x01c17000
+#define SUNXI_SATA_BASE 0x01c18000
+#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#define SUNXI_PATA_BASE 0x01c19000
+#define SUNXI_ACE_BASE 0x01c1a000
+#define SUNXI_TVE1_BASE 0x01c1b000
+#define SUNXI_USB2_BASE 0x01c1c000
+#else
+#define SUNXI_USB0_BASE 0x01c19000
+#define SUNXI_USB1_BASE 0x01c1a000
+#define SUNXI_USB2_BASE 0x01c1b000
+#endif
+#define SUNXI_CSI1_BASE 0x01c1d000
+#define SUNXI_TZASC_BASE 0x01c1e000
+#define SUNXI_SPI3_BASE 0x01c1f000
+
+#define SUNXI_CCM_BASE 0x01c20000
+#define SUNXI_INTC_BASE 0x01c20400
+#define SUNXI_PIO_BASE 0x01c20800
+#define SUNXI_TIMER_BASE 0x01c20c00
+#define SUNXI_SPDIF_BASE 0x01c21000
+#define SUNXI_AC97_BASE 0x01c21400
+#define SUNXI_IR0_BASE 0x01c21800
+#define SUNXI_IR1_BASE 0x01c21c00
+
+#define SUNXI_IIS_BASE 0x01c22400
+#define SUNXI_LRADC_BASE 0x01c22800
+#define SUNXI_AD_DA_BASE 0x01c22c00
+#define SUNXI_KEYPAD_BASE 0x01c23000
+#define SUNXI_TZPC_BASE 0x01c23400
+#define SUNXI_SID_BASE 0x01c23800
+#define SUNXI_SJTAG_BASE 0x01c23c00
+
+#define SUNXI_TP_BASE 0x01c25000
+#define SUNXI_PMU_BASE 0x01c25400
+#define SUN7I_CPUCFG_BASE 0x01c25c00
+
+#define SUNXI_UART0_BASE 0x01c28000
+#define SUNXI_UART1_BASE 0x01c28400
+#define SUNXI_UART2_BASE 0x01c28800
+#define SUNXI_UART3_BASE 0x01c28c00
+#define SUNXI_UART4_BASE 0x01c29000
+#define SUNXI_UART5_BASE 0x01c29400
+#define SUNXI_UART6_BASE 0x01c29800
+#define SUNXI_UART7_BASE 0x01c29c00
+#define SUNXI_PS2_0_BASE 0x01c2a000
+#define SUNXI_PS2_1_BASE 0x01c2a400
+
+#define SUNXI_TWI0_BASE 0x01c2ac00
+#define SUNXI_TWI1_BASE 0x01c2b000
+#define SUNXI_TWI2_BASE 0x01c2b400
+
+#define SUNXI_CAN_BASE 0x01c2bc00
+
+#define SUNXI_SCR_BASE 0x01c2c400
+
+#ifndef CONFIG_MACH_SUN6I
+#define SUNXI_GPS_BASE 0x01c30000
+#define SUNXI_MALI400_BASE 0x01c40000
+#define SUNXI_GMAC_BASE 0x01c50000
+#else
+#define SUNXI_GMAC_BASE 0x01c30000
+#endif
+
+#define SUNXI_DRAM_COM_BASE 0x01c62000
+#define SUNXI_DRAM_CTL0_BASE 0x01c63000
+#define SUNXI_DRAM_CTL1_BASE 0x01c64000
+#define SUNXI_DRAM_PHY0_BASE 0x01c65000
+#define SUNXI_DRAM_PHY1_BASE 0x01c66000
+
+/* module sram */
+#define SUNXI_SRAM_C_BASE 0x01d00000
+
+#define SUNXI_DE_FE0_BASE 0x01e00000
+#define SUNXI_DE_FE1_BASE 0x01e20000
+#define SUNXI_DE_BE0_BASE 0x01e60000
+#define SUNXI_DE_BE1_BASE 0x01e40000
+#define SUNXI_MP_BASE 0x01e80000
+#define SUNXI_AVG_BASE 0x01ea0000
+
+#define SUNXI_RTC_BASE 0x01f00000
+#define SUNXI_PRCM_BASE 0x01f01400
+#define SUN6I_CPUCFG_BASE 0x01f01c00
+#define SUNXI_R_UART_BASE 0x01f02800
+#define SUNXI_R_PIO_BASE 0x01f02c00
+#define SUN6I_P2WI_BASE 0x01f03400
+#define SUNXI_RSB_BASE 0x01f03400
+
+/* CoreSight Debug Module */
+#define SUNXI_CSDM_BASE 0x3f500000
+
+#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
+
+#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
+
+#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
+
+/* SS bonding ids used for cpu identification */
+#define SUNXI_SS_BOND_ID_A31 4
+#define SUNXI_SS_BOND_ID_A31S 5
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_ss_bonding_id(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SUNXI_CPU_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
new file mode 100644
index 0000000..04889c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -0,0 +1,109 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN9I_H
+#define _SUNXI_CPU_SUN9I_H
+
+#define REGS_AHB0_BASE 0x01C00000
+#define REGS_AHB1_BASE 0x00800000
+#define REGS_AHB2_BASE 0x03000000
+#define REGS_APB0_BASE 0x06000000
+#define REGS_APB1_BASE 0x07000000
+#define REGS_RCPUS_BASE 0x08000000
+
+#define SUNXI_SRAM_D_BASE 0x08100000
+
+/* AHB0 Module */
+#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
+#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
+
+#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
+#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
+#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
+#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
+#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
+
+#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000)
+#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000)
+#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000)
+#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000)
+
+#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
+#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
+#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
+
+/* AHB1 Module */
+#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000)
+#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000)
+#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000)
+#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000)
+#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000)
+
+/* AHB2 Module */
+#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
+#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000)
+#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
+#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
+#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
+
+#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
+#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
+#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000)
+
+#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000)
+#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000)
+#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000)
+#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000)
+
+#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
+#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
+#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
+#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000)
+/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */
+#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100)
+#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000)
+
+/* APB0 Module */
+#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
+#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
+#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
+#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00)
+#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400)
+#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800)
+
+/* APB1 Module */
+#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000)
+#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400)
+#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800)
+#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00)
+#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000)
+#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400)
+#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800)
+#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00)
+#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000)
+#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400)
+#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800)
+
+/* RCPUS Module */
+#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800)
+#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00)
+#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400)
+
+/* Misc. */
+#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */
+#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUN9I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
index 2ac8a87..5e94253 100644
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -9,6 +9,107 @@
#ifndef _SUNXI_DISPLAY_H
#define _SUNXI_DISPLAY_H
+struct sunxi_de_fe_reg {
+ u32 enable; /* 0x000 */
+ u32 frame_ctrl; /* 0x004 */
+ u32 bypass; /* 0x008 */
+ u32 algorithm_sel; /* 0x00c */
+ u32 line_int_ctrl; /* 0x010 */
+ u8 res0[0x0c]; /* 0x014 */
+ u32 ch0_addr; /* 0x020 */
+ u32 ch1_addr; /* 0x024 */
+ u32 ch2_addr; /* 0x028 */
+ u32 field_sequence; /* 0x02c */
+ u32 ch0_offset; /* 0x030 */
+ u32 ch1_offset; /* 0x034 */
+ u32 ch2_offset; /* 0x038 */
+ u8 res1[0x04]; /* 0x03c */
+ u32 ch0_stride; /* 0x040 */
+ u32 ch1_stride; /* 0x044 */
+ u32 ch2_stride; /* 0x048 */
+ u32 input_fmt; /* 0x04c */
+ u32 ch3_addr; /* 0x050 */
+ u32 ch4_addr; /* 0x054 */
+ u32 ch5_addr; /* 0x058 */
+ u32 output_fmt; /* 0x05c */
+ u32 int_enable; /* 0x060 */
+ u32 int_status; /* 0x064 */
+ u32 status; /* 0x068 */
+ u8 res2[0x04]; /* 0x06c */
+ u32 csc_coef00; /* 0x070 */
+ u32 csc_coef01; /* 0x074 */
+ u32 csc_coef02; /* 0x078 */
+ u32 csc_coef03; /* 0x07c */
+ u32 csc_coef10; /* 0x080 */
+ u32 csc_coef11; /* 0x084 */
+ u32 csc_coef12; /* 0x088 */
+ u32 csc_coef13; /* 0x08c */
+ u32 csc_coef20; /* 0x090 */
+ u32 csc_coef21; /* 0x094 */
+ u32 csc_coef22; /* 0x098 */
+ u32 csc_coef23; /* 0x09c */
+ u32 deinterlace_ctrl; /* 0x0a0 */
+ u32 deinterlace_diag; /* 0x0a4 */
+ u32 deinterlace_tempdiff; /* 0x0a8 */
+ u32 deinterlace_sawtooth; /* 0x0ac */
+ u32 deinterlace_spatcomp; /* 0x0b0 */
+ u32 deinterlace_burstlen; /* 0x0b4 */
+ u32 deinterlace_preluma; /* 0x0b8 */
+ u32 deinterlace_tile_addr; /* 0x0bc */
+ u32 deinterlace_tile_stride; /* 0x0c0 */
+ u8 res3[0x0c]; /* 0x0c4 */
+ u32 wb_stride_enable; /* 0x0d0 */
+ u32 ch3_stride; /* 0x0d4 */
+ u32 ch4_stride; /* 0x0d8 */
+ u32 ch5_stride; /* 0x0dc */
+ u32 fe_3d_ctrl; /* 0x0e0 */
+ u32 fe_3d_ch0_addr; /* 0x0e4 */
+ u32 fe_3d_ch1_addr; /* 0x0e8 */
+ u32 fe_3d_ch2_addr; /* 0x0ec */
+ u32 fe_3d_ch0_offset; /* 0x0f0 */
+ u32 fe_3d_ch1_offset; /* 0x0f4 */
+ u32 fe_3d_ch2_offset; /* 0x0f8 */
+ u8 res4[0x04]; /* 0x0fc */
+ u32 ch0_insize; /* 0x100 */
+ u32 ch0_outsize; /* 0x104 */
+ u32 ch0_horzfact; /* 0x108 */
+ u32 ch0_vertfact; /* 0x10c */
+ u32 ch0_horzphase; /* 0x110 */
+ u32 ch0_vertphase0; /* 0x114 */
+ u32 ch0_vertphase1; /* 0x118 */
+ u8 res5[0x04]; /* 0x11c */
+ u32 ch0_horztapoffset0; /* 0x120 */
+ u32 ch0_horztapoffset1; /* 0x124 */
+ u32 ch0_verttapoffset; /* 0x128 */
+ u8 res6[0xd4]; /* 0x12c */
+ u32 ch1_insize; /* 0x200 */
+ u32 ch1_outsize; /* 0x204 */
+ u32 ch1_horzfact; /* 0x208 */
+ u32 ch1_vertfact; /* 0x20c */
+ u32 ch1_horzphase; /* 0x210 */
+ u32 ch1_vertphase0; /* 0x214 */
+ u32 ch1_vertphase1; /* 0x218 */
+ u8 res7[0x04]; /* 0x21c */
+ u32 ch1_horztapoffset0; /* 0x220 */
+ u32 ch1_horztapoffset1; /* 0x224 */
+ u32 ch1_verttapoffset; /* 0x228 */
+ u8 res8[0x1d4]; /* 0x22c */
+ u32 ch0_horzcoef0[32]; /* 0x400 */
+ u32 ch0_horzcoef1[32]; /* 0x480 */
+ u32 ch0_vertcoef[32]; /* 0x500 */
+ u8 res9[0x80]; /* 0x580 */
+ u32 ch1_horzcoef0[32]; /* 0x600 */
+ u32 ch1_horzcoef1[32]; /* 0x680 */
+ u32 ch1_vertcoef[32]; /* 0x700 */
+ u8 res10[0x280]; /* 0x780 */
+ u32 vpp_enable; /* 0xa00 */
+ u32 vpp_dcti; /* 0xa04 */
+ u32 vpp_lp1; /* 0xa08 */
+ u32 vpp_lp2; /* 0xa0c */
+ u32 vpp_wle; /* 0xa10 */
+ u32 vpp_ble; /* 0xa14 */
+};
+
struct sunxi_de_be_reg {
u8 res0[0x800]; /* 0x000 */
u32 mode; /* 0x800 */
@@ -210,6 +311,20 @@ struct sunxi_tve_reg {
};
/*
+ * DE-FE register constants.
+ */
+#define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0)
+#define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16)
+#define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16)
+#define SUNXI_DE_FE_ENABLE_EN (1 << 0)
+#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0)
+#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1)
+#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16)
+#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1)
+#define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151
+#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002
+
+/*
* DE-BE register constants.
*/
#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
@@ -219,6 +334,7 @@ struct sunxi_tve_reg {
#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
+#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002
#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
/*
@@ -249,9 +365,7 @@ struct sunxi_tve_reg {
#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16)
#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0 (0 << 28)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60 (1 << 28)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE120 (2 << 28)
+#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28)
#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
index 6c1ec5b..40c385a 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h
@@ -76,7 +76,7 @@ struct dram_para {
u32 cas;
u32 zq;
u32 odt_en;
- u32 size;
+ u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */
u32 tpr0;
u32 tpr1;
u32 tpr2;
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 71cc879..f2c247d 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -45,9 +45,13 @@
*
* sun8i has 1 bank:
* PL0 - PL11
+ *
+ * sun9i has 3 banks:
+ * PL0 - PL9 | PM0 - PM15 | PN0 - PN1
*/
#define SUNXI_GPIO_L 11
#define SUNXI_GPIO_M 12
+#define SUNXI_GPIO_N 13
struct sunxi_gpio {
u32 cfg[4];
@@ -114,6 +118,7 @@ enum sunxi_gpio_number {
SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
SUNXI_GPIO_L_START = 352,
SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
+ SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M),
SUNXI_GPIO_AXP0_START = 1024,
};
@@ -129,6 +134,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
+#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr))
#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr))
@@ -187,6 +193,9 @@ enum sunxi_gpio_number {
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
+#define SUN9I_GPN0_R_RSB_SCK 3
+#define SUN9I_GPN1_R_RSB_SDA 3
+
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 537f145..74833b5 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,10 +43,11 @@ struct sunxi_mmc {
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+ defined(CONFIG_MACH_SUN9I)
u32 res2[64];
#endif
- u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */
+ u32 fifo; /* 0x100 / 0x200 FIFO access address */
};
#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
@@ -123,5 +124,8 @@ struct sunxi_mmc {
#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
+#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
+#define SUNXI_MMC_COMMON_RESET (1 << 18)
+
struct mmc *sunxi_mmc_init(int sdc_no);
#endif /* _SUNXI_MMC_H */
diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h
index 95a595a..a893466 100644
--- a/arch/arm/include/asm/arch-sunxi/rsb.h
+++ b/arch/arm/include/asm/arch-sunxi/rsb.h
@@ -37,6 +37,7 @@ struct sunxi_rsb_reg {
#define RSB_STAT_TERR_INT (1 << 1)
#define RSB_STAT_LBSY_INT (1 << 2)
+#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00
#define RSB_DMCR_DEVICE_MODE_START (1 << 31)
#define RSB_CMD_BYTE_WRITE 0x4e
@@ -46,8 +47,7 @@ struct sunxi_rsb_reg {
#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16)
#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0)
-void rsb_init(void);
-int rsb_set_device_mode(u32 device_mode_data);
+int rsb_init(void);
int rsb_set_device_address(u16 device_addr, u16 runtime_addr);
int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h
index 8d20973..cb538cd 100644
--- a/arch/arm/include/asm/arch-sunxi/usbc.h
+++ b/arch/arm/include/asm/arch-sunxi/usbc.h
@@ -11,6 +11,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+extern const struct musb_platform_ops sunxi_musb_ops;
+
void *sunxi_usbc_get_io_base(int index);
int sunxi_usbc_request_resources(int index);
int sunxi_usbc_free_resources(int index);
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index 84e7b55..a20bdaa 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -10,6 +10,7 @@
#define __TEGRA_MMC_H_
#include <fdtdec.h>
+#include <asm/gpio.h>
/* for mmc_config definition */
#include <mmc.h>
@@ -134,9 +135,9 @@ struct mmc_host {
int enabled; /* 1 to enable, 0 to disable */
int width; /* Bus Width, 1, 4 or 8 */
enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */
- struct fdt_gpio_state cd_gpio; /* Change Detect GPIO */
- struct fdt_gpio_state pwr_gpio; /* Power GPIO */
- struct fdt_gpio_state wp_gpio; /* Write Protect GPIO */
+ struct gpio_desc cd_gpio; /* Change Detect GPIO */
+ struct gpio_desc pwr_gpio; /* Power GPIO */
+ struct gpio_desc wp_gpio; /* Write Protect GPIO */
unsigned int version; /* SDHCI spec. version */
unsigned int clock; /* Current clock (MHz) */
struct mmc_config cfg; /* mmc configuration */
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h
index a04c84e..6feeda3 100644
--- a/arch/arm/include/asm/arch-tegra20/display.h
+++ b/arch/arm/include/asm/arch-tegra20/display.h
@@ -10,6 +10,7 @@
#include <asm/arch/dc.h>
#include <fdtdec.h>
+#include <asm/gpio.h>
/* This holds information about a window which can be displayed */
struct disp_ctl_win {
@@ -72,10 +73,10 @@ struct fdt_panel_config {
int pwm_channel; /* PWM channel to use for backlight */
enum lcd_cache_t cache_type;
- struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */
- struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */
- struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */
- struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */
+ struct gpio_desc backlight_en; /* GPIO for backlight enable */
+ struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */
+ struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */
+ struct gpio_desc panel_vdd; /* GPIO for panel vdd */
/*
* Panel required timings
* Timing 1: delay between panel_vdd-rise and data-rise
diff --git a/arch/arm/include/asm/arch-uniphier/boot-device.h b/arch/arm/include/asm/arch-uniphier/boot-device.h
index 6987f57..7a10f1c 100644
--- a/arch/arm/include/asm/arch-uniphier/boot-device.h
+++ b/arch/arm/include/asm/arch-uniphier/boot-device.h
@@ -8,7 +8,7 @@
#ifndef _ASM_BOOT_DEVICE_H_
#define _ASM_BOOT_DEVICE_H_
-u32 get_boot_mode_sel(void);
+int get_boot_mode_sel(void);
struct boot_device_info {
u32 type;
diff --git a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
index 484559c..6b7d600 100644
--- a/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/ddrphy-regs.h
@@ -72,7 +72,7 @@ struct ddrphy {
u32 gtr; /* General Timing Register */
u32 rsv[3]; /* Reserved */
} dx[9];
-} __packed;
+};
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/arch-uniphier/sg-regs.h b/arch/arm/include/asm/arch-uniphier/sg-regs.h
index fa5e6ae..4ae67c8 100644
--- a/arch/arm/include/asm/arch-uniphier/sg-regs.h
+++ b/arch/arm/include/asm/arch-uniphier/sg-regs.h
@@ -25,22 +25,29 @@
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
-#define SG_MEMCONF_CH0_SIZE_64MB ((0x0 << 10) | (0x01 << 0))
-#define SG_MEMCONF_CH0_SIZE_128MB ((0x0 << 10) | (0x02 << 0))
-#define SG_MEMCONF_CH0_SIZE_256MB ((0x0 << 10) | (0x03 << 0))
-#define SG_MEMCONF_CH0_SIZE_512MB ((0x1 << 10) | (0x00 << 0))
-#define SG_MEMCONF_CH0_SIZE_1024MB ((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
+#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
+#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
+#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
-#define SG_MEMCONF_CH1_SIZE_64MB ((0x0 << 11) | (0x01 << 2))
-#define SG_MEMCONF_CH1_SIZE_128MB ((0x0 << 11) | (0x02 << 2))
-#define SG_MEMCONF_CH1_SIZE_256MB ((0x0 << 11) | (0x03 << 2))
-#define SG_MEMCONF_CH1_SIZE_512MB ((0x1 << 11) | (0x00 << 2))
-#define SG_MEMCONF_CH1_SIZE_1024MB ((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
+#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
+#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
+#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
+#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
+#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
+#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
+#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
+#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
+
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
@@ -101,6 +108,7 @@
#else
#include <linux/types.h>
+#include <linux/sizes.h>
#include <asm/io.h>
static inline void sg_set_pinsel(int n, int value)
@@ -111,24 +119,24 @@ static inline void sg_set_pinsel(int n, int value)
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
- int size_mb = (size >> 20) / num;
+ int size_mb = size / num;
u32 ret;
switch (size_mb) {
- case 64:
- ret = SG_MEMCONF_CH0_SIZE_64MB;
+ case SZ_64M:
+ ret = SG_MEMCONF_CH0_SZ_64M;
break;
- case 128:
- ret = SG_MEMCONF_CH0_SIZE_128MB;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH0_SZ_128M;
break;
- case 256:
- ret = SG_MEMCONF_CH0_SIZE_256MB;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH0_SZ_256M;
break;
- case 512:
- ret = SG_MEMCONF_CH0_SIZE_512MB;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH0_SZ_512M;
break;
- case 1024:
- ret = SG_MEMCONF_CH0_SIZE_1024MB;
+ case SZ_1G:
+ ret = SG_MEMCONF_CH0_SZ_1G;
break;
default:
BUG();
@@ -151,24 +159,24 @@ static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
- int size_mb = (size >> 20) / num;
+ int size_mb = size / num;
u32 ret;
switch (size_mb) {
- case 64:
- ret = SG_MEMCONF_CH1_SIZE_64MB;
+ case SZ_64M:
+ ret = SG_MEMCONF_CH1_SZ_64M;
break;
- case 128:
- ret = SG_MEMCONF_CH1_SIZE_128MB;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH1_SZ_128M;
break;
- case 256:
- ret = SG_MEMCONF_CH1_SIZE_256MB;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH1_SZ_256M;
break;
- case 512:
- ret = SG_MEMCONF_CH1_SIZE_512MB;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH1_SZ_512M;
break;
- case 1024:
- ret = SG_MEMCONF_CH1_SIZE_1024MB;
+ case SZ_1G:
+ ret = SG_MEMCONF_CH1_SZ_1G;
break;
default:
BUG();
@@ -188,6 +196,43 @@ static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
}
return ret;
}
+
+static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
+{
+ int size_mb = size / num;
+ u32 ret;
+
+ switch (size_mb) {
+ case SZ_64M:
+ ret = SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ ret = SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ ret = SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ ret = SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ BUG();
+ break;
+ }
+
+ switch (num) {
+ case 1:
+ ret |= SG_MEMCONF_CH2_NUM_1;
+ break;
+ case 2:
+ ret |= SG_MEMCONF_CH2_NUM_2;
+ break;
+ default:
+ BUG();
+ break;
+ }
+ return ret;
+}
#endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */
diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
index 2dbba75..a26ae87 100644
--- a/arch/arm/include/asm/arch-zynq/gpio.h
+++ b/arch/arm/include/asm/arch-zynq/gpio.h
@@ -7,19 +7,4 @@
#ifndef _ZYNQ_GPIO_H
#define _ZYNQ_GPIO_H
-inline int gpio_get_value(unsigned gpio)
-{
- return 0;
-}
-
-inline int gpio_set_value(unsigned gpio, int val)
-{
- return 0;
-}
-
-inline int gpio_request(unsigned gpio, const char *label)
-{
- return 0;
-}
-
#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h
index 2aede0c..e2e0b73 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -21,6 +21,9 @@
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
+#define ZYNQ_QSPI_BASEADDR 0xE000D000
+#define ZYNQ_SMC_BASEADDR 0xE000E000
+#define ZYNQ_NAND_BASEADDR 0xE1000000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
#define ZYNQ_USB_BASEADDR0 0xE0002000
@@ -28,7 +31,9 @@
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0x7
+#define ZYNQ_BM_QSPI 0x1
#define ZYNQ_BM_NOR 0x2
+#define ZYNQ_BM_NAND 0x4
#define ZYNQ_BM_SD 0x5
#define ZYNQ_BM_JTAG 0x0
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h
index 89c47f3..9d50e24 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/include/asm/arch-zynq/sys_proto.h
@@ -20,7 +20,7 @@ extern void zynq_ddrc_init(void);
extern unsigned int zynq_get_silicon_version(void);
/* Driver extern functions */
-extern int zynq_sdhci_init(u32 regbase);
+extern int zynq_sdhci_init(phys_addr_t regbase);
extern int zynq_sdhci_of_init(const void *blob);
extern void ps7_init(void);
diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h
index f97f3dd..414042d 100644
--- a/arch/arm/include/asm/u-boot-arm.h
+++ b/arch/arm/include/asm/u-boot-arm.h
@@ -36,7 +36,6 @@ int arch_early_init_r(void);
/* board/.../... */
int board_init(void);
-int dram_init (void);
void dram_init_banksize (void);
/* cpu/.../interrupt.c */