summaryrefslogtreecommitdiff
path: root/arch/arm/include
diff options
context:
space:
mode:
authorTom Rini <trini@ti.com>2012-07-30 14:49:50 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:13 +0200
commitd4898ea89684aa285cfb34fbab6831c28dc0ed33 (patch)
treed7413e876f856972cb78e98b854f9fe9826d426e /arch/arm/include
parent318f27c98fc9c07df983d4214ef723331181e7db (diff)
downloadu-boot-imx-d4898ea89684aa285cfb34fbab6831c28dc0ed33.zip
u-boot-imx-d4898ea89684aa285cfb34fbab6831c28dc0ed33.tar.gz
u-boot-imx-d4898ea89684aa285cfb34fbab6831c28dc0ed33.tar.bz2
am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and support
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 0526863..6b22c45 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -47,6 +47,23 @@
#define DDR2_PHY_RANK0_DELAY 0x1
#define DDR2_IOCTRL_VALUE 0x18B
+/* Micron MT41J128M16JT-125 */
+#define DDR3_EMIF_READ_LATENCY 0x06
+#define DDR3_EMIF_TIM1 0x0888A39B
+#define DDR3_EMIF_TIM2 0x26337FDA
+#define DDR3_EMIF_TIM3 0x501F830F
+#define DDR3_EMIF_SDCFG 0x61C04AB2
+#define DDR3_EMIF_SDREF 0x0000093B
+#define DDR3_ZQ_CFG 0x50074BE4
+#define DDR3_DLL_LOCK_DIFF 0x1
+#define DDR3_RATIO 0x40
+#define DDR3_INVERT_CLKOUT 0x1
+#define DDR3_RD_DQS 0x3B
+#define DDR3_WR_DQS 0x85
+#define DDR3_PHY_WR_DATA 0xC1
+#define DDR3_PHY_FIFO_WE 0x100
+#define DDR3_IOCTRL_VALUE 0x18B
+
/**
* Configure SDRAM
*/