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| author | Simon Glass <sjg@chromium.org> | 2011-08-30 06:23:15 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-04 11:36:15 +0200 |
| commit | d07dc4993d646a1b1857a987f9145bf0a8c21370 (patch) | |
| tree | bc7ed6722b7cfd6e7ba52520fb34a17b80a03d01 /arch/arm/include | |
| parent | 858bd095e1583f86af93ac1ae8f9e28aebbd0aa5 (diff) | |
| download | u-boot-imx-d07dc4993d646a1b1857a987f9145bf0a8c21370.zip u-boot-imx-d07dc4993d646a1b1857a987f9145bf0a8c21370.tar.gz u-boot-imx-d07dc4993d646a1b1857a987f9145bf0a8c21370.tar.bz2 | |
Tegra2: Use clock and pinmux functions to simplify code
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra2/clk_rst.h | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h index a574c53..bd9d9ad 100644 --- a/arch/arm/include/asm/arch-tegra2/clk_rst.h +++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h @@ -140,43 +140,6 @@ struct clk_rst_ctlr { uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ }; -#define PLL_BYPASS (1 << 31) -#define PLL_ENABLE (1 << 30) -#define PLL_BASE_OVRRIDE (1 << 28) -#define PLL_DIVP_VALUE (1 << 20) /* post divider, b22:20 */ -#define PLL_DIVM_VALUE 0x0C /* input divider, b4:0 */ - -#define SWR_UARTD_RST (1 << 1) -#define CLK_ENB_UARTD (1 << 1) -#define SWR_UARTA_RST (1 << 6) -#define CLK_ENB_UARTA (1 << 6) - -#define SWR_CPU_RST (1 << 0) -#define CLK_ENB_CPU (1 << 0) -#define SWR_CSITE_RST (1 << 9) -#define CLK_ENB_CSITE (1 << 9) - -#define SET_CPURESET0 (1 << 0) -#define SET_DERESET0 (1 << 4) -#define SET_DBGRESET0 (1 << 12) - -#define SET_CPURESET1 (1 << 1) -#define SET_DERESET1 (1 << 5) -#define SET_DBGRESET1 (1 << 13) - -#define CLR_CPURESET0 (1 << 0) -#define CLR_DERESET0 (1 << 4) -#define CLR_DBGRESET0 (1 << 12) - -#define CLR_CPURESET1 (1 << 1) -#define CLR_DERESET1 (1 << 5) -#define CLR_DBGRESET1 (1 << 13) - -#define CPU0_CLK_STP (1 << 8) -#define CPU1_CLK_STP (1 << 9) - -#define CPCON (1 << 8) - /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ #define CPU1_CLK_STP_SHIFT 9 |