ARM: OMAP4+: Clean up the pmic code

The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>

5 files changed, 28 insertions, 11 deletions

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index ceb3367..ed7a1c8 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -242,11 +242,6 @@
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-
 struct omap4_scrm_regs {
 	u32 revision;           /* 0x0000 */
 	u32 pad00[63];
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 1c0ce9b..73edd9d 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -180,7 +180,8 @@ struct control_lpddr2io_regs {
 #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR	(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
 
 /* ROM code defines */
 /* Boot device */
diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 063347f..15362ae 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -234,8 +234,4 @@
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
 #endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 7123694..4bf555a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -273,7 +273,8 @@ struct omap_sys_ctrl_regs {
 #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
 #define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
+#define OMAP5_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x20)
 
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0xFFFFFFFF
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index c2d8388..eee6893 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -364,10 +364,31 @@ struct dplls {
 	const struct dpll_params *usb;
 };
 
+struct pmic_data {
+	u32 base_offset;
+	u32 step;
+	u32 start_code;
+	unsigned gpio;
+	int gpio_en;
+};
+
+struct volts {
+	u32 value;
+	u32 addr;
+	struct pmic_data *pmic;
+};
+
+struct vcores_data {
+	struct volts mpu;
+	struct volts core;
+	struct volts mm;
+};
+
 extern struct prcm_regs const **prcm;
 extern struct prcm_regs const omap5_es1_prcm;
 extern struct prcm_regs const omap4_prcm;
 extern struct dplls const **dplls_data;
+extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];
 
 void hw_data_init(void);
@@ -391,6 +412,9 @@ u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
 void enable_basic_uboot_clocks(void);
 void enable_non_essential_clocks(void);
+void scale_vcores(struct vcores_data const *);
+u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
+void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
 
 /* Max value for DPLL multiplier M */
 #define OMAP_DPLL_MAX_N	127