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| author | Richard Zhu <r65037@freescale.com> | 2014-07-15 14:19:03 +0800 |
|---|---|---|
| committer | Richard Zhu <r65037@freescale.com> | 2014-07-31 15:17:00 +0800 |
| commit | ec78595a24b5ff1020baa97b6d6e79a3a3326307 (patch) | |
| tree | ddb3512104efc1056df8fe1e6d145be363fcb672 /arch/arm/include | |
| parent | a09f718e5ace202dd14426a030268ea11c7a9ba5 (diff) | |
| download | u-boot-imx-ec78595a24b5ff1020baa97b6d6e79a3a3326307.zip u-boot-imx-ec78595a24b5ff1020baa97b6d6e79a3a3326307.tar.gz u-boot-imx-ec78595a24b5ff1020baa97b6d6e79a3a3326307.tar.bz2 | |
ENGR00325255 pcie:enable pcie support on imx6sx sd
Enable pcie support in uboot on imx6sx sd boards
- enable_pcie_clock should be call before ssp_en is set,
since that ssp_en control the phy_ref clk gate, turn on
it after the source of the pcie clks are stable.
- add debug info
- add rx_eq of gpr12 on imx6sx
- there are random link down issue on imx6sx. It's
pcie ep reset issue.
solution:reset ep, then retry link can fix it.
Signed-off-by: Richard Zhu <r65037@freescale.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/iomux.h | 11 |
2 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 1692866..fad04f6 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -1104,6 +1104,8 @@ extern void check_cpu_temperature(void); #ifdef CONFIG_MX6SX extern void vadc_power_up(void); extern void vadc_power_down(void); +extern void pcie_power_up(void); +extern void pcie_power_off(void); #endif /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index c3003c1..dba2186 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -19,6 +19,12 @@ #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) /* + * IOMUXC_GPR5 bit fields + */ +#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) +#define IOMUXC_GPR5_PCIE_PERST (1 << 18) + +/* * IOMUXC_GPR8 bit fields */ #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) @@ -35,12 +41,15 @@ /* * IOMUXC_GPR12 bit fields */ +#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0) +#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) -#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12) +#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) +#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) /* * IOMUXC_GPR13 bit fields |