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authorStefan Roese <sr@denx.de>2013-04-17 00:32:43 +0000
committerStefano Babic <sbabic@denx.de>2013-04-22 10:26:40 +0200
commitb29ca4a15888eb8eb98313f8c6ca6f329b22ef37 (patch)
tree9ff8f9cdef3dcb84fa05c2e31e91b4e87e621341 /arch/arm/include
parentae695b18df7c19ec3d062e36c1c25864096146f8 (diff)
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imx: Add titanium board support (i.MX6 based)
Titanium is a i.MX6 based board from ProjectionDesign / Barco. This patch adds support for this board with the newly introduced NAND support for i.MX6. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index b1ed62f..df6f09f 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -267,10 +267,13 @@ struct mxc_ccm_reg {
/* Define the bits in register CS2CDR */
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
+#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
+#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
+#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
@@ -420,8 +423,8 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
-#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
-#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
+#define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
+#define MXC_CCM_CCGR0_APBHDMA_MASK (3<<MXC_CCM_CCGR0_APBHDMA_OFFSET)
#define MXC_CCM_CCGR0_ASRC_OFFSET 6
#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8