arm, davinci: da850/dm365 lowlevel cleanup

- Cleanup a lot of fix values, and use defines instead.
- Also make some values configurable through the board config
  file.
- delete the NAND_SPL code for da850, as it is not used actually
- remove the asm code

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

6 files changed, 42 insertions, 1 deletions

diff --git a/arch/arm/include/asm/arch-davinci/aintc_defs.h b/arch/arm/include/asm/arch-davinci/aintc_defs.h
index 8f37053..38f814c 100644
--- a/arch/arm/include/asm/arch-davinci/aintc_defs.h
+++ b/arch/arm/include/asm/arch-davinci/aintc_defs.h
@@ -47,4 +47,6 @@ struct dv_aintc_regs {
 
 #define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
 
+#define DV_AINTC_INTCTL_IDMODE	(1 << 2)
+
 #endif /* _DV_AINTC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
index 22a92a3..e489c47 100644
--- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
+++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
@@ -36,7 +36,7 @@ void da850_waitloop(unsigned long loopcnt);
 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
 void da850_lpc_transition(unsigned char pscnum, unsigned char module,
 		unsigned char domain, unsigned char state);
-int da850_ddr_setup(unsigned int freq);
+int da850_ddr_setup(void);
 void da850_psc_init(void);
 void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
 	unsigned long value);
diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
index 1b9430c..4f943b8 100644
--- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h
+++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h
@@ -63,6 +63,7 @@ struct dv_ddr2_regs_ctrl {
 
 #define DV_DDR_SDTMR2_RASMAX_SHIFT	27
 #define DV_DDR_SDTMR2_XP_SHIFT	25
+#define DV_DDR_SDTMR2_ODT_SHIFT	23
 #define DV_DDR_SDTMR2_XSNR_SHIFT	16
 #define DV_DDR_SDTMR2_XSRD_SHIFT	8
 #define DV_DDR_SDTMR2_RTP_SHIFT	5
@@ -84,6 +85,9 @@ struct dv_ddr2_regs_ctrl {
 #define DV_DDR_SDCR_IBANK_SHIFT	4
 #define DV_DDR_SDCR_PAGESIZE_SHIFT	0
 
+#define DV_DDR_SDRCR_LPMODEN	(1 << 31)
+#define DV_DDR_SDRCR_MCLKSTOPEN	(1 << 30)
+
 #define DV_DDR_SRCR_LPMODEN_SHIFT	31
 #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT	30
 
diff --git a/arch/arm/include/asm/arch-davinci/emif_defs.h b/arch/arm/include/asm/arch-davinci/emif_defs.h
index b48ec17..b9e78a5 100644
--- a/arch/arm/include/asm/arch-davinci/emif_defs.h
+++ b/arch/arm/include/asm/arch-davinci/emif_defs.h
@@ -70,6 +70,7 @@ struct davinci_emif_regs {
 #define DAVINCI_NANDFCR_1BIT_ECC_START(n)		(1 << (8 + (n-2)))
 #define DAVINCI_NANDFCR_4BIT_ECC_START			(1 << 12)
 #define DAVINCI_NANDFCR_4BIT_CALC_START			(1 << 13)
+#define DAVINCI_NANDFCR_CS2NAND				(1 << 0)
 
 /* Chip Select setup */
 #define DAVINCI_ABCR_STROBE_SELECT			(1 << 31)
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index ee8fd43..f80f312 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -230,6 +230,9 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_LPSC_CFG5		38
 #define DAVINCI_LPSC_GEM		39
 #define DAVINCI_LPSC_IMCOP		40
+#define DAVINCI_LPSC_VPSSMASTER		47
+#define DAVINCI_LPSC_MJCP		50
+#define DAVINCI_LPSC_HDVICP		51
 
 #define DAVINCI_DM646X_LPSC_EMAC	14
 #define DAVINCI_DM646X_LPSC_UART0	26
@@ -385,6 +388,20 @@ struct davinci_psc_regs {
 #define PINMUX3				0x01c4000c
 #define PINMUX4				0x01c40010
 
+struct davinci_uart_ctrl_regs {
+	dv_reg	revid1;
+	dv_reg	res;
+	dv_reg	pwremu_mgmt;
+	dv_reg	mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE	(1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST	(1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST	(1 << 14)
+
 #else /* CONFIG_SOC_DA8XX */
 
 struct davinci_pllc_regs {
@@ -492,6 +509,9 @@ struct davinci_syscfg1_regs {
 #define VTP_READY		(1 << 15)
 #define VTP_IOPWRDWN		(1 << 14)
 
+#define DV_SYSCFG_KICK0_UNLOCK	0x83e70b13
+#define DV_SYSCFG_KICK1_UNLOCK	0x95a4f1e0
+
 /* Interrupt controller */
 struct davinci_aintc_regs {
 	dv_reg	revid;
diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index 5c30953..f1396e3 100644
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -57,11 +57,24 @@ struct dv_pll_regs {
 	unsigned int	plldiv9;	/* 0x174 */
 };
 
+#define PLL_MASTER_LOCK	(1 << 4)
+
+#define PLLCTL_CLOCK_MODE_SHIFT	8
 #define PLLCTL_PLLEN	(1 << 0)
 #define PLLCTL_PLLPWRDN	(1 << 1)
 #define PLLCTL_PLLRST	(1 << 3)
+#define PLLCTL_PLLDIS	(1 << 4)
 #define PLLCTL_PLLENSRC	(1 << 5)
 #define PLLCTL_RES_9	(1 << 8)
+#define PLLCTL_EXTCLKSRC	(1 << 9)
+
+#define PLL_POSTDEN	(1 << 15)
+
+#define PLL_SCSCFG3_DIV45PENA	(1 << 2)
+#define PLL_SCSCFG3_EMA_CLKSRC	(1 << 1)
+
+#define PLL_RSTYPE_POR		(1 << 0)
+#define PLL_RSTYPE_XWRST	(1 << 1)
 
 #define PLLSECCTL_TINITZ	(1 << 16)
 #define PLLSECCTL_TENABLE	(1 << 17)
@@ -69,6 +82,7 @@ struct dv_pll_regs {
 #define PLLSECCTL_STOPMODE	(1 << 22)
 
 #define PLLCMD_GOSET		(1 << 0)
+#define PLLCMD_GOSTAT		(1 << 0)
 
 #define PLL0_LOCK		0x07000000
 #define PLL1_LOCK		0x07000000