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| author | Tom Rini <trini@ti.com> | 2014-07-07 21:40:16 -0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-07-25 16:26:08 -0400 |
| commit | c4f80f500356a8e0a71debe5bbe6e9a0d6d5d62e (patch) | |
| tree | 29f973053d1afac41e1f69c43d083f473bc40853 /arch/arm/include | |
| parent | c6ac7e3bdc195a7dd39b5bf699deceedb9444c0c (diff) | |
| download | u-boot-imx-c4f80f500356a8e0a71debe5bbe6e9a0d6d5d62e.zip u-boot-imx-c4f80f500356a8e0a71debe5bbe6e9a0d6d5d62e.tar.gz u-boot-imx-c4f80f500356a8e0a71debe5bbe6e9a0d6d5d62e.tar.bz2 | |
am335x_evm / gumstix pepper: Correct DDR settings
As noted by clang, we have been shifting certain values out of 32bit
range when setting some DDR registers. Upon further inspection these
had been touching reserved fields (and having no impact). These came in
from historical bring-up code and can be discarded. Similarly, we had
been declaring some fields as 0 when they will be initialized that way.
Tested on Beaglebone White.
Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-By: Ash Charles <ashcharles@gmail.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 4d89952..97bbfe2 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -33,11 +33,7 @@ #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a #define MT47H128M16RT25E_RATIO 0x80 -#define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 -#define MT47H128M16RT25E_WR_DQS 0x00 -#define MT47H128M16RT25E_PHY_WRLVL 0x00 -#define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B |