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author | Roger Quadros <rogerq@ti.com> | 2013-11-11 16:56:40 +0200 |
---|---|---|
committer | Tom Rini <trini@ti.com> | 2013-12-04 08:12:09 -0500 |
commit | 8ffcf74bb057d049c379b2bdc126871c81215ec3 (patch) | |
tree | 8b8c4279e5a7cdc1c55b31eab38af10e9dd682b9 /arch/arm/include | |
parent | 9c4b64fb612e3129823ba83691e08f4c6d2042ea (diff) | |
download | u-boot-imx-8ffcf74bb057d049c379b2bdc126871c81215ec3.zip u-boot-imx-8ffcf74bb057d049c379b2bdc126871c81215ec3.tar.gz u-boot-imx-8ffcf74bb057d049c379b2bdc126871c81215ec3.tar.bz2 |
ARM: OMAP5: Add PRCM and Control information for SATA
Adds the necessary PRCM and Control register information for
SATA on OMAP5.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-omap5/omap.h | 3 | ||||
-rw-r--r-- | arch/arm/include/asm/omap_common.h | 2 |
3 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 8869b50..2dfe4ef 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -137,6 +137,9 @@ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +/* CM_L3INIT_SATA_CLKCTRL */ +#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) + /* CM_WKUP_GPTIMER1_CLKCTRL */ #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index f1d1160..590235b 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -64,6 +64,9 @@ /* QSPI */ #define QSPI_BASE 0x4B300000 +/* SATA */ +#define DWC_AHSATA_BASE 0x4A140000 + /* * Hardware Register Details */ diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 0219d6c..a78f990 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -226,6 +226,7 @@ struct prcm_regs { u32 cm_l3init_hsusbotg_clkctrl; u32 cm_l3init_hsusbtll_clkctrl; u32 cm_l3init_p1500_clkctrl; + u32 cm_l3init_sata_clkctrl; u32 cm_l3init_fsusb_clkctrl; u32 cm_l3init_ocp2scp1_clkctrl; u32 cm_l3init_ocp2scp3_clkctrl; @@ -366,6 +367,7 @@ struct omap_sys_ctrl_regs { u32 control_ldosram_mpu_voltage_ctrl; u32 control_ldosram_core_voltage_ctrl; u32 control_usbotghs_ctrl; + u32 control_phy_power_sata; u32 control_padconf_core_base; u32 control_paconf_global; u32 control_paconf_mode; |