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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-01-14 15:21:00 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-01-14 15:21:00 +0100
commit1199c377cf14c240b903e351ab02b3b2cd3800c6 (patch)
tree8ea274860fc5d3d7a011c2896d865b6976008384 /arch/arm/include
parent961ffc7759b703e1c574280267e705f2e5f54432 (diff)
parente4660e0b7363cdc86519f4af2143b841592a7ffd (diff)
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Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-exynos/clk.h1
-rw-r--r--arch/arm/include/asm/arch-exynos/clock.h276
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h48
-rw-r--r--arch/arm/include/asm/arch-exynos/dp_info.h2
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h85
-rw-r--r--arch/arm/include/asm/arch-exynos/mipi_dsim.h7
-rw-r--r--arch/arm/include/asm/arch-exynos/periph.h33
-rw-r--r--arch/arm/include/asm/arch-exynos/pinmux.h8
-rw-r--r--arch/arm/include/asm/arch-exynos/sromc.h18
9 files changed, 459 insertions, 19 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index cd12323..1935b0b 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -34,6 +34,7 @@ unsigned long get_arm_clk(void);
unsigned long get_i2c_clk(void);
unsigned long get_pwm_clk(void);
unsigned long get_uart_clk(int dev_index);
+unsigned long get_mmc_clk(int dev_index);
void set_mmc_clk(int dev_index, unsigned int div);
unsigned long get_lcd_clk(void);
void set_lcd_clk(void);
diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index ff6781a..9b56b4e 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -251,6 +251,282 @@ struct exynos4_clock {
unsigned int div_iem_l1;
};
+struct exynos4x12_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned int gate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned int clkout_leftbus;
+ unsigned int clkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned int gate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned int clkout_rightbus;
+ unsigned int clkout_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned int epll_lock;
+ unsigned char res16[0xc];
+ unsigned int vpll_lock;
+ unsigned char res17[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned int epll_con2;
+ unsigned char res18[0x4];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned int vpll_con2;
+ unsigned char res19[0xe4];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res20[0x8];
+ unsigned int src_cam;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned char res21[0x4];
+ unsigned int src_lcd;
+ unsigned int src_isp;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res22[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned int src_cam1;
+ unsigned char res23[0xb4];
+ unsigned int src_mask_top;
+ unsigned char res24[0xc];
+ unsigned int src_mask_cam;
+ unsigned int src_mask_tv;
+ unsigned char res25[0xc];
+ unsigned int src_mask_lcd;
+ unsigned int src_mask_isp;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res26[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res27[0xb8];
+ unsigned int mux_stat_top0;
+ unsigned int mux_stat_top1;
+ unsigned char res28[0x10];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned char res29[0x28];
+ unsigned int mux_stat_cam1;
+ unsigned char res30[0xb4];
+ unsigned int div_top;
+ unsigned char res31[0xc];
+ unsigned int div_cam;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned char res32[0x4];
+ unsigned int div_lcd;
+ unsigned int div_isp;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned int div_cam1;
+ unsigned char res33[0x14];
+ unsigned int div2_ratio;
+ unsigned char res34[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res35[0xc];
+ unsigned int div_stat_cam;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned char res36[0x4];
+ unsigned int div_stat_lcd;
+ unsigned int div_stat_isp;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned int div_stat_cam1;
+ unsigned char res37[0x14];
+ unsigned int div2_stat;
+ unsigned char res38[0x29c];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned char res39[0x4];
+ unsigned int gate_ip_lcd;
+ unsigned int gate_ip_isp;
+ unsigned char res40[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res41[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res42[0xc];
+ unsigned char res43[0x4];
+ unsigned char res44[0xc];
+ unsigned int gate_block;
+ unsigned char res45[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res46[0x3600];
+ unsigned int mpll_lock;
+ unsigned char res47[0xfc];
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res48[0xf0];
+ unsigned int src_dmc;
+ unsigned char res49[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res50[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res51[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res52[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res53[0xf8];
+ unsigned int gate_bus_dmc0;
+ unsigned int gate_bus_dmc1;
+ unsigned char res54[0x1f8];
+ unsigned int gate_ip_dmc0;
+ unsigned int gate_ip_dmc1;
+ unsigned char res55[0xf8];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res56[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res57[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res58[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res59[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res60[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res61[0x8];
+ unsigned int dmc_freq_ctrl;
+ unsigned int dmc_pause_ctrl;
+ unsigned int dddrphy_lock_ctrl;
+ unsigned int c2c_state;
+ unsigned char res62[0x2f60];
+ unsigned int apll_lock;
+ unsigned char res63[0x8];
+ unsigned char res64[0xf4];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned char res65[0xf8];
+ unsigned int src_cpu;
+ unsigned char res66[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res67[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res68[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res69[0x2f8];
+ unsigned int clk_gate_ip_cpu;
+ unsigned char res70[0xfc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res71[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res72[0x10];
+ unsigned char res73[0x8];
+ unsigned int pwr_ctrl;
+ unsigned int pwr_ctrl2;
+ unsigned char res74[0xd8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res75[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res76[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+ unsigned char res77[0xe0];
+ unsigned int l2_status;
+ unsigned char res78[0xc];
+ unsigned int cpu_status;
+ unsigned char res79[0xc];
+ unsigned int ptm_status;
+ unsigned char res80[0x2edc];
+ unsigned int div_isp0;
+ unsigned int div_isp1;
+ unsigned char res81[0xf8];
+ unsigned int div_stat_isp0;
+ unsigned int div_stat_isp1;
+ unsigned char res82[0x3f8];
+ unsigned int gate_ip_isp0;
+ unsigned int gate_ip_isp1;
+ unsigned char res83[0x1f8];
+ unsigned int clkout_cmu_isp;
+ unsigned int clkout_cmu_ispd_div_stat;
+ unsigned char res84[0xf8];
+ unsigned int cmu_isp_spar0;
+ unsigned int cmu_isp_spar1;
+ unsigned int cmu_isp_spar2;
+ unsigned int cmu_isp_spar3;
+};
+
struct exynos5_clock {
unsigned int apll_lock;
unsigned char res1[0xfc];
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index f06af2e..eb34422 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -27,7 +27,7 @@
#define EXYNOS_CPU_NAME "Exynos"
#define EXYNOS4_ADDR_BASE 0x10000000
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
#define EXYNOS4_I2C_SPACING 0x10000
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
@@ -63,7 +63,40 @@
#define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
-/* EXYNOS5 */
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
+#define EXYNOS4X12_PRO_ID 0x10000000
+#define EXYNOS4X12_SYSREG_BASE 0x10010000
+#define EXYNOS4X12_POWER_BASE 0x10020000
+#define EXYNOS4X12_SWRESET 0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
+#define EXYNOS4X12_CLOCK_BASE 0x10030000
+#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
+#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
+#define EXYNOS4X12_DMC0_BASE 0x10600000
+#define EXYNOS4X12_DMC1_BASE 0x10610000
+#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
+#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_FIMD_BASE 0x11C00000
+#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
+#define EXYNOS4X12_USBOTG_BASE 0x12480000
+#define EXYNOS4X12_MMC_BASE 0x12510000
+#define EXYNOS4X12_SROMC_BASE 0x12570000
+#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
+#define EXYNOS4X12_USBPHY_BASE 0x125B0000
+#define EXYNOS4X12_UART_BASE 0x13800000
+#define EXYNOS4X12_I2C_BASE 0x13860000
+#define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
+
+#define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING 0x10000
#define EXYNOS5_GPIO_PART4_BASE 0x03860000
@@ -154,17 +187,20 @@ static inline int proid_is_##type(void) \
}
IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
{ \
- if (cpu_is_exynos4()) \
+ if (cpu_is_exynos4()) { \
+ if (proid_is_exynos4412()) \
+ return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
- else if (cpu_is_exynos5()) \
+ } else if (cpu_is_exynos5()) { \
return EXYNOS5_##base; \
- else \
- return 0; \
+ } \
+ return 0; \
}
SAMSUNG_BASE(adc, ADC_BASE)
diff --git a/arch/arm/include/asm/arch-exynos/dp_info.h b/arch/arm/include/asm/arch-exynos/dp_info.h
index 3569498..102b709 100644
--- a/arch/arm/include/asm/arch-exynos/dp_info.h
+++ b/arch/arm/include/asm/arch-exynos/dp_info.h
@@ -211,4 +211,6 @@ unsigned int exynos_init_dp(void)
}
#endif
+void exynos_set_dp_platform_data(struct exynos_dp_platform_data *pd);
+
#endif /* _DP_INFO_H */
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index 4db8fd6..cfe1024 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -79,6 +79,67 @@ struct exynos4_gpio_part3 {
struct s5p_gpio_bank z;
};
+struct exynos4x12_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank res1[0x5];
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank res2[0x2];
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+};
+
+struct exynos4x12_gpio_part2 {
+ struct s5p_gpio_bank res1[0x2];
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+ struct s5p_gpio_bank res2[0x3];
+ struct s5p_gpio_bank m0;
+ struct s5p_gpio_bank m1;
+ struct s5p_gpio_bank m2;
+ struct s5p_gpio_bank m3;
+ struct s5p_gpio_bank m4;
+ struct s5p_gpio_bank res3[0x48];
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct exynos4x12_gpio_part3 {
+ struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part4 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[0x1];
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+ struct s5p_gpio_bank res2[0x1];
+ struct s5p_gpio_bank v4;
+};
+
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
@@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
+#define exynos4x12_gpio_part1_get_nr(bank, pin) \
+ ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
+ EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
+ - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part2_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
+ EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
+ - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
+
+#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part3_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
+ EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
+ - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
+
#define exynos5_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
EXYNOS5_GPIO_PART1_BASE)->bank)) \
diff --git a/arch/arm/include/asm/arch-exynos/mipi_dsim.h b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
index 9a7cbeb..c1c9a35 100644
--- a/arch/arm/include/asm/arch-exynos/mipi_dsim.h
+++ b/arch/arm/include/asm/arch-exynos/mipi_dsim.h
@@ -358,7 +358,14 @@ struct mipi_dsim_lcd_driver {
void (*mipi_display_on)(struct mipi_dsim_device *dsim_dev);
};
+#ifdef CONFIG_EXYNOS_MIPI_DSIM
int exynos_mipi_dsi_init(void);
+#else
+static inline int exynos_mipi_dsi_init(void)
+{
+ return 0;
+}
+#endif
/*
* register mipi_dsim_lcd_driver object defined by lcd panel driver
diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h
index 13abd2d..89bcdfc 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -25,12 +25,17 @@
#define __ASM_ARM_ARCH_PERIPH_H
/*
- * Peripherals requiring clock/pinmux configuration. List will
+ * Peripherals required for pinmux configuration. List will
* grow with support for more devices getting added.
+ * Numbering based on interrupt table.
*
*/
enum periph_id {
- PERIPH_ID_I2C0,
+ PERIPH_ID_UART0 = 51,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_I2C0 = 56,
PERIPH_ID_I2C1,
PERIPH_ID_I2C2,
PERIPH_ID_I2C3,
@@ -38,22 +43,24 @@ enum periph_id {
PERIPH_ID_I2C5,
PERIPH_ID_I2C6,
PERIPH_ID_I2C7,
- PERIPH_ID_I2S1,
- PERIPH_ID_SDMMC0,
+ PERIPH_ID_SPI0 = 68,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_SDMMC0 = 75,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC2,
PERIPH_ID_SDMMC3,
- PERIPH_ID_SDMMC4,
- PERIPH_ID_SROMC,
- PERIPH_ID_SPI0,
- PERIPH_ID_SPI1,
- PERIPH_ID_SPI2,
+ PERIPH_ID_I2S1 = 99,
+
+ /* Since following peripherals do
+ * not have shared peripheral interrupts (SPIs)
+ * they are numbered arbitiraly after the maximum
+ * SPIs Exynos has (128)
+ */
+ PERIPH_ID_SROMC = 128,
PERIPH_ID_SPI3,
PERIPH_ID_SPI4,
- PERIPH_ID_UART0,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
- PERIPH_ID_UART3,
+ PERIPH_ID_SDMMC4,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h
index 10ea736..014eebc 100644
--- a/arch/arm/include/asm/arch-exynos/pinmux.h
+++ b/arch/arm/include/asm/arch-exynos/pinmux.h
@@ -55,4 +55,12 @@ enum {
*/
int exynos_pinmux_config(int peripheral, int flags);
+/**
+ * Decode the peripheral id using the interrpt numbers.
+ *
+ * @param blob Device tree blob
+ * @param node FDT I2C node to find
+ * @return peripheral id if ok, PERIPH_ID_NONE on error
+ */
+int pinmux_decode_periph_id(const void *blob, int node);
#endif
diff --git a/arch/arm/include/asm/arch-exynos/sromc.h b/arch/arm/include/asm/arch-exynos/sromc.h
index f616bcb..dc6aae2 100644
--- a/arch/arm/include/asm/arch-exynos/sromc.h
+++ b/arch/arm/include/asm/arch-exynos/sromc.h
@@ -48,4 +48,22 @@ struct s5p_sromc {
/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+enum {
+ FDT_SROM_PMC,
+ FDT_SROM_TACP,
+ FDT_SROM_TAH,
+ FDT_SROM_TCOH,
+ FDT_SROM_TACC,
+ FDT_SROM_TCOS,
+ FDT_SROM_TACS,
+
+ FDT_SROM_TIMING_COUNT,
+};
+
+struct fdt_sromc {
+ u8 bank; /* srom bank number */
+ u8 width; /* bus width in bytes */
+ unsigned int timing[FDT_SROM_TIMING_COUNT]; /* timing parameters */
+};
+
#endif /* __ASM_ARCH_SROMC_H_ */