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| author | Vaibhav Hiremath <hvaibhav@ti.com> | 2012-03-08 17:15:47 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2012-10-25 11:30:22 -0700 |
| commit | 000820b5835c2b8b863af992b66dc973dc4bd202 (patch) | |
| tree | f6abab9e0b1e696f8a21a8e7defbf6bd0fae0ee6 /arch/arm/include/asm | |
| parent | 3530a35d747508e98976a1d86a6d3f9b31cb3fd2 (diff) | |
| download | u-boot-imx-000820b5835c2b8b863af992b66dc973dc4bd202.zip u-boot-imx-000820b5835c2b8b863af992b66dc973dc4bd202.tar.gz u-boot-imx-000820b5835c2b8b863af992b66dc973dc4bd202.tar.bz2 | |
am335x: Enable RTC 32K OSC clock
In order to support low power state, you must source kernel system
timers to persistent clock, available across suspend/resume. In case of
AM335x device, the only source we have is, RTC32K, available in
wakeup/always-on domain. Having said that, during validation it has
been observed that, RTC clock need couple of seconds delay to stabilize
the RTC OSC clock; and such a huge delay is not acceptable in kernel
especially during early init and also it will impact quick/fast boot
use-cases.
So, RTC32k OSC enable dependency has been shifted to
SPL/first-bootloader.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/cpu.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware.h | 4 |
2 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 6cfbef7..819fd2f 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -169,6 +169,12 @@ struct cm_dpll { unsigned int clktimer2clk; /* offset 0x08 */ }; +/* Control Module RTC registers */ +struct cm_rtc { + unsigned int rtcclkctrl; /* offset 0x0 */ + unsigned int clkstctrl; /* offset 0x4 */ +}; + /* Watchdog timer registers */ struct wd_timer { unsigned int resv1[4]; @@ -218,6 +224,15 @@ struct gptimer { unsigned int tcar2; /* offset 0x58 */ }; +/* RTC Registers */ +struct rtc_regs { + unsigned int res[21]; + unsigned int osc; /* offset 0x54 */ + unsigned int res2[5]; + unsigned int kick0r; /* offset 0x6c */ + unsigned int kick1r; /* offset 0x70 */ +}; + /* UART Registers */ struct uart_sys { unsigned int resv1[21]; diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 62332f2..5bd4bc8 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -61,6 +61,7 @@ #define CM_WKUP 0x44E00400 #define CM_DPLL 0x44E00500 #define CM_DEVICE 0x44E00700 +#define CM_RTC 0x44E00800 #define CM_CEFUSE 0x44E00A00 #define PRM_DEVICE 0x44E00F00 @@ -83,4 +84,7 @@ #define AM335X_CPSW_BASE 0x4A100000 #define AM335X_CPSW_MDIO_BASE 0x4A101000 +/* RTC base address */ +#define AM335X_RTC_BASE 0x44E3E000 + #endif /* __AM33XX_HARDWARE_H */ |