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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2015-11-05 12:00:14 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-11-30 09:11:12 -0800 |
| commit | b4017364630fbc526bbf5e917d8fae6013805488 (patch) | |
| tree | ea2df6ef79c7526db3f91e1cfb06803b3e96aebd /arch/arm/include/asm | |
| parent | 5380335e66e7d731bd417f0fe6fcee68750b0245 (diff) | |
| download | u-boot-imx-b4017364630fbc526bbf5e917d8fae6013805488.zip u-boot-imx-b4017364630fbc526bbf5e917d8fae6013805488.tar.gz u-boot-imx-b4017364630fbc526bbf5e917d8fae6013805488.tar.bz2 | |
armv8: ls2085a: Add workaround of errata A009635
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 9 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index afc329a..b5a2d28 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -98,11 +98,20 @@ #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) +#define DCSR_CGACRE5 0x700070914ULL +#define EPU_EPCMPR5 0x700060914ULL +#define EPU_EPCCR5 0x700060814ULL +#define EPU_EPSMCR5 0x700060228ULL +#define EPU_EPECR5 0x700060314ULL +#define EPU_EPCTR5 0x700060a14ULL +#define EPU_EPGCR 0x700060000ULL + #define CONFIG_SYS_FSL_ERRATUM_A008336 #define CONFIG_SYS_FSL_ERRATUM_A008511 #define CONFIG_SYS_FSL_ERRATUM_A008514 #define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 +#define CONFIG_SYS_FSL_ERRATUM_A009635 #elif defined(CONFIG_LS1043A) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_CACHELINE_SIZE 64 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 8691906..504c1f9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -58,4 +58,7 @@ void fsl_lsch2_early_init_f(void); #endif void cpu_name(char *name); +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635 +void erratum_a009635(void); +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ |