Merge branch 'master' of git://git.denx.de/u-boot-arm

21 files changed, 3188 insertions, 1661 deletions

diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 7637457..f00fad3 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -42,6 +42,8 @@
 #define MODULE_CLKCTRL_IDLEST_DISABLED		3
 
 /* CM_CLKMODE_DPLL */
+#define CM_CLKMODE_DPLL_SSC_EN_SHIFT		12
+#define CM_CLKMODE_DPLL_SSC_EN_MASK		(1 << 12)
 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT		11
 #define CM_CLKMODE_DPLL_REGM4XEN_MASK		(1 << 11)
 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT		10
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h
index fdf73b5..ba71714 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -98,7 +98,7 @@
 #define EXYNOS5_I2C_SPACING		0x10000
 
 #define EXYNOS5_AUDIOSS_BASE		0x03810000
-#define EXYNOS5_GPIO_PART4_BASE		0x03860000
+#define EXYNOS5_GPIO_PART8_BASE		0x03860000
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000
@@ -108,9 +108,13 @@
 #define EXYNOS5_WATCHDOG_BASE		0x101D0000
 #define EXYNOS5_ACE_SFR_BASE		0x10830000
 #define EXYNOS5_DMC_PHY_BASE		0x10C00000
-#define EXYNOS5_GPIO_PART3_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART5_BASE		0x10D10000
+#define EXYNOS5_GPIO_PART6_BASE		0x10D10060
+#define EXYNOS5_GPIO_PART7_BASE		0x10D100C0
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_GPIO_PART2_BASE		0x114002E0
+#define EXYNOS5_GPIO_PART3_BASE		0x11400C00
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_USB_HOST_XHCI_BASE	0x12000000
 #define EXYNOS5_USB3PHY_BASE		0x12100000
@@ -125,7 +129,7 @@
 #define EXYNOS5_I2S_BASE		0x12D60000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
 #define EXYNOS5_SPI_ISP_BASE		0x131A0000
-#define EXYNOS5_GPIO_PART2_BASE		0x13400000
+#define EXYNOS5_GPIO_PART4_BASE		0x13400000
 #define EXYNOS5_FIMD_BASE		0x14400000
 #define EXYNOS5_DP_BASE			0x145B0000
 
@@ -135,7 +139,7 @@
 
 /* EXYNOS5420 */
 #define EXYNOS5420_AUDIOSS_BASE		0x03810000
-#define EXYNOS5420_GPIO_PART5_BASE	0x03860000
+#define EXYNOS5420_GPIO_PART6_BASE	0x03860000
 #define EXYNOS5420_PRO_ID		0x10000000
 #define EXYNOS5420_CLOCK_BASE		0x10010000
 #define EXYNOS5420_POWER_BASE		0x10040000
@@ -158,8 +162,9 @@
 #define EXYNOS5420_PWMTIMER_BASE	0x12DD0000
 #define EXYNOS5420_SPI_ISP_BASE		0x131A0000
 #define EXYNOS5420_GPIO_PART2_BASE	0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE	0x13410000
-#define EXYNOS5420_GPIO_PART4_BASE	0x14000000
+#define EXYNOS5420_GPIO_PART3_BASE	0x13400C00
+#define EXYNOS5420_GPIO_PART4_BASE	0x13410000
+#define EXYNOS5420_GPIO_PART5_BASE	0x14000000
 #define EXYNOS5420_GPIO_PART1_BASE	0x14010000
 #define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
 #define EXYNOS5420_DP_BASE		0x145B0000
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h
index d6868fa..be5113f 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -19,328 +19,1515 @@ struct s5p_gpio_bank {
 	unsigned char	res1[8];
 };
 
-struct exynos4_gpio_part1 {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank b;
-	struct s5p_gpio_bank c0;
-	struct s5p_gpio_bank c1;
-	struct s5p_gpio_bank d0;
-	struct s5p_gpio_bank d1;
-	struct s5p_gpio_bank e0;
-	struct s5p_gpio_bank e1;
-	struct s5p_gpio_bank e2;
-	struct s5p_gpio_bank e3;
-	struct s5p_gpio_bank e4;
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank f2;
-	struct s5p_gpio_bank f3;
-};
+/* GPIO pins per bank  */
+#define GPIO_PER_BANK 8
 
-struct exynos4_gpio_part2 {
-	struct s5p_gpio_bank j0;
-	struct s5p_gpio_bank j1;
-	struct s5p_gpio_bank k0;
-	struct s5p_gpio_bank k1;
-	struct s5p_gpio_bank k2;
-	struct s5p_gpio_bank k3;
-	struct s5p_gpio_bank l0;
-	struct s5p_gpio_bank l1;
-	struct s5p_gpio_bank l2;
-	struct s5p_gpio_bank y0;
-	struct s5p_gpio_bank y1;
-	struct s5p_gpio_bank y2;
-	struct s5p_gpio_bank y3;
-	struct s5p_gpio_bank y4;
-	struct s5p_gpio_bank y5;
-	struct s5p_gpio_bank y6;
-	struct s5p_gpio_bank res1[80];
-	struct s5p_gpio_bank x0;
-	struct s5p_gpio_bank x1;
-	struct s5p_gpio_bank x2;
-	struct s5p_gpio_bank x3;
-};
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos4_gpio_pin {
+	/* GPIO_PART1_STARTS */
+	EXYNOS4_GPIO_A00,		/* 0 */
+	EXYNOS4_GPIO_A01,
+	EXYNOS4_GPIO_A02,
+	EXYNOS4_GPIO_A03,
+	EXYNOS4_GPIO_A04,
+	EXYNOS4_GPIO_A05,
+	EXYNOS4_GPIO_A06,
+	EXYNOS4_GPIO_A07,
+	EXYNOS4_GPIO_A10,		/* 8 */
+	EXYNOS4_GPIO_A11,
+	EXYNOS4_GPIO_A12,
+	EXYNOS4_GPIO_A13,
+	EXYNOS4_GPIO_A14,
+	EXYNOS4_GPIO_A15,
+	EXYNOS4_GPIO_A16,
+	EXYNOS4_GPIO_A17,
+	EXYNOS4_GPIO_B0,		/* 16 0x10 */
+	EXYNOS4_GPIO_B1,
+	EXYNOS4_GPIO_B2,
+	EXYNOS4_GPIO_B3,
+	EXYNOS4_GPIO_B4,
+	EXYNOS4_GPIO_B5,
+	EXYNOS4_GPIO_B6,
+	EXYNOS4_GPIO_B7,
+	EXYNOS4_GPIO_C00,		/* 24 0x18 */
+	EXYNOS4_GPIO_C01,
+	EXYNOS4_GPIO_C02,
+	EXYNOS4_GPIO_C03,
+	EXYNOS4_GPIO_C04,
+	EXYNOS4_GPIO_C05,
+	EXYNOS4_GPIO_C06,
+	EXYNOS4_GPIO_C07,
+	EXYNOS4_GPIO_C10,		/* 32 0x20*/
+	EXYNOS4_GPIO_C11,
+	EXYNOS4_GPIO_C12,
+	EXYNOS4_GPIO_C13,
+	EXYNOS4_GPIO_C14,
+	EXYNOS4_GPIO_C15,
+	EXYNOS4_GPIO_C16,
+	EXYNOS4_GPIO_C17,
+	EXYNOS4_GPIO_D00,		/* 40 0x28 */
+	EXYNOS4_GPIO_D01,
+	EXYNOS4_GPIO_D02,
+	EXYNOS4_GPIO_D03,
+	EXYNOS4_GPIO_D04,
+	EXYNOS4_GPIO_D05,
+	EXYNOS4_GPIO_D06,
+	EXYNOS4_GPIO_D07,
+	EXYNOS4_GPIO_D10,		/* 48 0x30 */
+	EXYNOS4_GPIO_D11,
+	EXYNOS4_GPIO_D12,
+	EXYNOS4_GPIO_D13,
+	EXYNOS4_GPIO_D14,
+	EXYNOS4_GPIO_D15,
+	EXYNOS4_GPIO_D16,
+	EXYNOS4_GPIO_D17,
+	EXYNOS4_GPIO_E00,		/* 56 0x38 */
+	EXYNOS4_GPIO_E01,
+	EXYNOS4_GPIO_E02,
+	EXYNOS4_GPIO_E03,
+	EXYNOS4_GPIO_E04,
+	EXYNOS4_GPIO_E05,
+	EXYNOS4_GPIO_E06,
+	EXYNOS4_GPIO_E07,
+	EXYNOS4_GPIO_E10,		/* 64 0x40 */
+	EXYNOS4_GPIO_E11,
+	EXYNOS4_GPIO_E12,
+	EXYNOS4_GPIO_E13,
+	EXYNOS4_GPIO_E14,
+	EXYNOS4_GPIO_E15,
+	EXYNOS4_GPIO_E16,
+	EXYNOS4_GPIO_E17,
+	EXYNOS4_GPIO_E20,		/* 72 0x48 */
+	EXYNOS4_GPIO_E21,
+	EXYNOS4_GPIO_E22,
+	EXYNOS4_GPIO_E23,
+	EXYNOS4_GPIO_E24,
+	EXYNOS4_GPIO_E25,
+	EXYNOS4_GPIO_E26,
+	EXYNOS4_GPIO_E27,
+	EXYNOS4_GPIO_E30,		/* 80 0x50 */
+	EXYNOS4_GPIO_E31,
+	EXYNOS4_GPIO_E32,
+	EXYNOS4_GPIO_E33,
+	EXYNOS4_GPIO_E34,
+	EXYNOS4_GPIO_E35,
+	EXYNOS4_GPIO_E36,
+	EXYNOS4_GPIO_E37,
+	EXYNOS4_GPIO_E40,		/* 88 0x58 */
+	EXYNOS4_GPIO_E41,
+	EXYNOS4_GPIO_E42,
+	EXYNOS4_GPIO_E43,
+	EXYNOS4_GPIO_E44,
+	EXYNOS4_GPIO_E45,
+	EXYNOS4_GPIO_E46,
+	EXYNOS4_GPIO_E47,
+	EXYNOS4_GPIO_F00,		/* 96 0x60 */
+	EXYNOS4_GPIO_F01,
+	EXYNOS4_GPIO_F02,
+	EXYNOS4_GPIO_F03,
+	EXYNOS4_GPIO_F04,
+	EXYNOS4_GPIO_F05,
+	EXYNOS4_GPIO_F06,
+	EXYNOS4_GPIO_F07,
+	EXYNOS4_GPIO_F10,		/* 104 0x68 */
+	EXYNOS4_GPIO_F11,
+	EXYNOS4_GPIO_F12,
+	EXYNOS4_GPIO_F13,
+	EXYNOS4_GPIO_F14,
+	EXYNOS4_GPIO_F15,
+	EXYNOS4_GPIO_F16,
+	EXYNOS4_GPIO_F17,
+	EXYNOS4_GPIO_F20,		/* 112 0x70 */
+	EXYNOS4_GPIO_F21,
+	EXYNOS4_GPIO_F22,
+	EXYNOS4_GPIO_F23,
+	EXYNOS4_GPIO_F24,
+	EXYNOS4_GPIO_F25,
+	EXYNOS4_GPIO_F26,
+	EXYNOS4_GPIO_F27,
+	EXYNOS4_GPIO_F30,		/* 120 0x78 */
+	EXYNOS4_GPIO_F31,
+	EXYNOS4_GPIO_F32,
+	EXYNOS4_GPIO_F33,
+	EXYNOS4_GPIO_F34,
+	EXYNOS4_GPIO_F35,
+	EXYNOS4_GPIO_F36,
+	EXYNOS4_GPIO_F37,
 
-struct exynos4_gpio_part3 {
-	struct s5p_gpio_bank z;
-};
+	/* GPIO_PART2_STARTS */
+	EXYNOS4_GPIO_MAX_PORT_PART_1,	/* 128 0x80 */
+	EXYNOS4_GPIO_J00 = EXYNOS4_GPIO_MAX_PORT_PART_1,
+	EXYNOS4_GPIO_J01,
+	EXYNOS4_GPIO_J02,
+	EXYNOS4_GPIO_J03,
+	EXYNOS4_GPIO_J04,
+	EXYNOS4_GPIO_J05,
+	EXYNOS4_GPIO_J06,
+	EXYNOS4_GPIO_J07,
+	EXYNOS4_GPIO_J10,		/* 136 0x88 */
+	EXYNOS4_GPIO_J11,
+	EXYNOS4_GPIO_J12,
+	EXYNOS4_GPIO_J13,
+	EXYNOS4_GPIO_J14,
+	EXYNOS4_GPIO_J15,
+	EXYNOS4_GPIO_J16,
+	EXYNOS4_GPIO_J17,
+	EXYNOS4_GPIO_K00,		/* 144 0x90 */
+	EXYNOS4_GPIO_K01,
+	EXYNOS4_GPIO_K02,
+	EXYNOS4_GPIO_K03,
+	EXYNOS4_GPIO_K04,
+	EXYNOS4_GPIO_K05,
+	EXYNOS4_GPIO_K06,
+	EXYNOS4_GPIO_K07,
+	EXYNOS4_GPIO_K10,		/* 152 0x98 */
+	EXYNOS4_GPIO_K11,
+	EXYNOS4_GPIO_K12,
+	EXYNOS4_GPIO_K13,
+	EXYNOS4_GPIO_K14,
+	EXYNOS4_GPIO_K15,
+	EXYNOS4_GPIO_K16,
+	EXYNOS4_GPIO_K17,
+	EXYNOS4_GPIO_K20,		/* 160 0xA0 */
+	EXYNOS4_GPIO_K21,
+	EXYNOS4_GPIO_K22,
+	EXYNOS4_GPIO_K23,
+	EXYNOS4_GPIO_K24,
+	EXYNOS4_GPIO_K25,
+	EXYNOS4_GPIO_K26,
+	EXYNOS4_GPIO_K27,
+	EXYNOS4_GPIO_K30,		/* 168 0xA8 */
+	EXYNOS4_GPIO_K31,
+	EXYNOS4_GPIO_K32,
+	EXYNOS4_GPIO_K33,
+	EXYNOS4_GPIO_K34,
+	EXYNOS4_GPIO_K35,
+	EXYNOS4_GPIO_K36,
+	EXYNOS4_GPIO_K37,
+	EXYNOS4_GPIO_L00,		/* 176 0xB0 */
+	EXYNOS4_GPIO_L01,
+	EXYNOS4_GPIO_L02,
+	EXYNOS4_GPIO_L03,
+	EXYNOS4_GPIO_L04,
+	EXYNOS4_GPIO_L05,
+	EXYNOS4_GPIO_L06,
+	EXYNOS4_GPIO_L07,
+	EXYNOS4_GPIO_L10,		/* 184 0xB8 */
+	EXYNOS4_GPIO_L11,
+	EXYNOS4_GPIO_L12,
+	EXYNOS4_GPIO_L13,
+	EXYNOS4_GPIO_L14,
+	EXYNOS4_GPIO_L15,
+	EXYNOS4_GPIO_L16,
+	EXYNOS4_GPIO_L17,
+	EXYNOS4_GPIO_L20,		/* 192 0xC0 */
+	EXYNOS4_GPIO_L21,
+	EXYNOS4_GPIO_L22,
+	EXYNOS4_GPIO_L23,
+	EXYNOS4_GPIO_L24,
+	EXYNOS4_GPIO_L25,
+	EXYNOS4_GPIO_L26,
+	EXYNOS4_GPIO_L27,
+	EXYNOS4_GPIO_Y00,		/* 200 0xC8 */
+	EXYNOS4_GPIO_Y01,
+	EXYNOS4_GPIO_Y02,
+	EXYNOS4_GPIO_Y03,
+	EXYNOS4_GPIO_Y04,
+	EXYNOS4_GPIO_Y05,
+	EXYNOS4_GPIO_Y06,
+	EXYNOS4_GPIO_Y07,
+	EXYNOS4_GPIO_Y10,		/* 208 0xD0 */
+	EXYNOS4_GPIO_Y11,
+	EXYNOS4_GPIO_Y12,
+	EXYNOS4_GPIO_Y13,
+	EXYNOS4_GPIO_Y14,
+	EXYNOS4_GPIO_Y15,
+	EXYNOS4_GPIO_Y16,
+	EXYNOS4_GPIO_Y17,
+	EXYNOS4_GPIO_Y20,		/* 216 0xD8 */
+	EXYNOS4_GPIO_Y21,
+	EXYNOS4_GPIO_Y22,
+	EXYNOS4_GPIO_Y23,
+	EXYNOS4_GPIO_Y24,
+	EXYNOS4_GPIO_Y25,
+	EXYNOS4_GPIO_Y26,
+	EXYNOS4_GPIO_Y27,
+	EXYNOS4_GPIO_Y30,		/* 224 0xE0 */
+	EXYNOS4_GPIO_Y31,
+	EXYNOS4_GPIO_Y32,
+	EXYNOS4_GPIO_Y33,
+	EXYNOS4_GPIO_Y34,
+	EXYNOS4_GPIO_Y35,
+	EXYNOS4_GPIO_Y36,
+	EXYNOS4_GPIO_Y37,
+	EXYNOS4_GPIO_Y40,		/* 232 0xE8 */
+	EXYNOS4_GPIO_Y41,
+	EXYNOS4_GPIO_Y42,
+	EXYNOS4_GPIO_Y43,
+	EXYNOS4_GPIO_Y44,
+	EXYNOS4_GPIO_Y45,
+	EXYNOS4_GPIO_Y46,
+	EXYNOS4_GPIO_Y47,
+	EXYNOS4_GPIO_Y50,		/* 240 0xF0 */
+	EXYNOS4_GPIO_Y51,
+	EXYNOS4_GPIO_Y52,
+	EXYNOS4_GPIO_Y53,
+	EXYNOS4_GPIO_Y54,
+	EXYNOS4_GPIO_Y55,
+	EXYNOS4_GPIO_Y56,
+	EXYNOS4_GPIO_Y57,
+	EXYNOS4_GPIO_Y60,		/* 248 0xF8 */
+	EXYNOS4_GPIO_Y61,
+	EXYNOS4_GPIO_Y62,
+	EXYNOS4_GPIO_Y63,
+	EXYNOS4_GPIO_Y64,
+	EXYNOS4_GPIO_Y65,
+	EXYNOS4_GPIO_Y66,
+	EXYNOS4_GPIO_Y67,
+	EXYNOS4_GPIO_X00 = 896,		/* 896 0x380 */
+	EXYNOS4_GPIO_X01,
+	EXYNOS4_GPIO_X02,
+	EXYNOS4_GPIO_X03,
+	EXYNOS4_GPIO_X04,
+	EXYNOS4_GPIO_X05,
+	EXYNOS4_GPIO_X06,
+	EXYNOS4_GPIO_X07,
+	EXYNOS4_GPIO_X10,		/* 904 0x388 */
+	EXYNOS4_GPIO_X11,
+	EXYNOS4_GPIO_X12,
+	EXYNOS4_GPIO_X13,
+	EXYNOS4_GPIO_X14,
+	EXYNOS4_GPIO_X15,
+	EXYNOS4_GPIO_X16,
+	EXYNOS4_GPIO_X17,
+	EXYNOS4_GPIO_X20,		/* 912 0x390 */
+	EXYNOS4_GPIO_X21,
+	EXYNOS4_GPIO_X22,
+	EXYNOS4_GPIO_X23,
+	EXYNOS4_GPIO_X24,
+	EXYNOS4_GPIO_X25,
+	EXYNOS4_GPIO_X26,
+	EXYNOS4_GPIO_X27,
+	EXYNOS4_GPIO_X30,		/* 920 0x398 */
+	EXYNOS4_GPIO_X31,
+	EXYNOS4_GPIO_X32,
+	EXYNOS4_GPIO_X33,
+	EXYNOS4_GPIO_X34,
+	EXYNOS4_GPIO_X35,
+	EXYNOS4_GPIO_X36,
+	EXYNOS4_GPIO_X37,
+
+	/* GPIO_PART3_STARTS */
+	EXYNOS4_GPIO_MAX_PORT_PART_2,	/* 928 0x3A0 */
+	EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+	EXYNOS4_GPIO_Z1,
+	EXYNOS4_GPIO_Z2,
+	EXYNOS4_GPIO_Z3,
+	EXYNOS4_GPIO_Z4,
+	EXYNOS4_GPIO_Z5,
+	EXYNOS4_GPIO_Z6,
+	EXYNOS4_GPIO_Z7,
 
-struct exynos4x12_gpio_part1 {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank b;
-	struct s5p_gpio_bank c0;
-	struct s5p_gpio_bank c1;
-	struct s5p_gpio_bank d0;
-	struct s5p_gpio_bank d1;
-	struct s5p_gpio_bank res1[0x5];
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank f2;
-	struct s5p_gpio_bank f3;
-	struct s5p_gpio_bank res2[0x2];
-	struct s5p_gpio_bank j0;
-	struct s5p_gpio_bank j1;
+	EXYNOS4_GPIO_MAX_PORT
 };
 
-struct exynos4x12_gpio_part2 {
-	struct s5p_gpio_bank res1[0x2];
-	struct s5p_gpio_bank k0;
-	struct s5p_gpio_bank k1;
-	struct s5p_gpio_bank k2;
-	struct s5p_gpio_bank k3;
-	struct s5p_gpio_bank l0;
-	struct s5p_gpio_bank l1;
-	struct s5p_gpio_bank l2;
-	struct s5p_gpio_bank y0;
-	struct s5p_gpio_bank y1;
-	struct s5p_gpio_bank y2;
-	struct s5p_gpio_bank y3;
-	struct s5p_gpio_bank y4;
-	struct s5p_gpio_bank y5;
-	struct s5p_gpio_bank y6;
-	struct s5p_gpio_bank res2[0x3];
-	struct s5p_gpio_bank m0;
-	struct s5p_gpio_bank m1;
-	struct s5p_gpio_bank m2;
-	struct s5p_gpio_bank m3;
-	struct s5p_gpio_bank m4;
-	struct s5p_gpio_bank res3[0x48];
-	struct s5p_gpio_bank x0;
-	struct s5p_gpio_bank x1;
-	struct s5p_gpio_bank x2;
-	struct s5p_gpio_bank x3;
+enum exynos4X12_gpio_pin {
+	/* GPIO_PART1_STARTS */
+	EXYNOS4X12_GPIO_A00,		/* 0 */
+	EXYNOS4X12_GPIO_A01,
+	EXYNOS4X12_GPIO_A02,
+	EXYNOS4X12_GPIO_A03,
+	EXYNOS4X12_GPIO_A04,
+	EXYNOS4X12_GPIO_A05,
+	EXYNOS4X12_GPIO_A06,
+	EXYNOS4X12_GPIO_A07,
+	EXYNOS4X12_GPIO_A10,		/* 8 */
+	EXYNOS4X12_GPIO_A11,
+	EXYNOS4X12_GPIO_A12,
+	EXYNOS4X12_GPIO_A13,
+	EXYNOS4X12_GPIO_A14,
+	EXYNOS4X12_GPIO_A15,
+	EXYNOS4X12_GPIO_A16,
+	EXYNOS4X12_GPIO_A17,
+	EXYNOS4X12_GPIO_B0,		/* 16 0x10 */
+	EXYNOS4X12_GPIO_B1,
+	EXYNOS4X12_GPIO_B2,
+	EXYNOS4X12_GPIO_B3,
+	EXYNOS4X12_GPIO_B4,
+	EXYNOS4X12_GPIO_B5,
+	EXYNOS4X12_GPIO_B6,
+	EXYNOS4X12_GPIO_B7,
+	EXYNOS4X12_GPIO_C00,		/* 24 0x18 */
+	EXYNOS4X12_GPIO_C01,
+	EXYNOS4X12_GPIO_C02,
+	EXYNOS4X12_GPIO_C03,
+	EXYNOS4X12_GPIO_C04,
+	EXYNOS4X12_GPIO_C05,
+	EXYNOS4X12_GPIO_C06,
+	EXYNOS4X12_GPIO_C07,
+	EXYNOS4X12_GPIO_C10,		/* 32 0x20 */
+	EXYNOS4X12_GPIO_C11,
+	EXYNOS4X12_GPIO_C12,
+	EXYNOS4X12_GPIO_C13,
+	EXYNOS4X12_GPIO_C14,
+	EXYNOS4X12_GPIO_C15,
+	EXYNOS4X12_GPIO_C16,
+	EXYNOS4X12_GPIO_C17,
+	EXYNOS4X12_GPIO_D00,		/* 40 0x28 */
+	EXYNOS4X12_GPIO_D01,
+	EXYNOS4X12_GPIO_D02,
+	EXYNOS4X12_GPIO_D03,
+	EXYNOS4X12_GPIO_D04,
+	EXYNOS4X12_GPIO_D05,
+	EXYNOS4X12_GPIO_D06,
+	EXYNOS4X12_GPIO_D07,
+	EXYNOS4X12_GPIO_D10,		/* 48 0x30 */
+	EXYNOS4X12_GPIO_D11,
+	EXYNOS4X12_GPIO_D12,
+	EXYNOS4X12_GPIO_D13,
+	EXYNOS4X12_GPIO_D14,
+	EXYNOS4X12_GPIO_D15,
+	EXYNOS4X12_GPIO_D16,
+	EXYNOS4X12_GPIO_D17,
+	EXYNOS4X12_GPIO_F00 = 96,	/* 96 0x60 */
+	EXYNOS4X12_GPIO_F01,
+	EXYNOS4X12_GPIO_F02,
+	EXYNOS4X12_GPIO_F03,
+	EXYNOS4X12_GPIO_F04,
+	EXYNOS4X12_GPIO_F05,
+	EXYNOS4X12_GPIO_F06,
+	EXYNOS4X12_GPIO_F07,
+	EXYNOS4X12_GPIO_F10,		/* 104 0x68 */
+	EXYNOS4X12_GPIO_F11,
+	EXYNOS4X12_GPIO_F12,
+	EXYNOS4X12_GPIO_F13,
+	EXYNOS4X12_GPIO_F14,
+	EXYNOS4X12_GPIO_F15,
+	EXYNOS4X12_GPIO_F16,
+	EXYNOS4X12_GPIO_F17,
+	EXYNOS4X12_GPIO_F20,		/* 112 0x70 */
+	EXYNOS4X12_GPIO_F21,
+	EXYNOS4X12_GPIO_F22,
+	EXYNOS4X12_GPIO_F23,
+	EXYNOS4X12_GPIO_F24,
+	EXYNOS4X12_GPIO_F25,
+	EXYNOS4X12_GPIO_F26,
+	EXYNOS4X12_GPIO_F27,
+	EXYNOS4X12_GPIO_F30,		/* 120 0x78 */
+	EXYNOS4X12_GPIO_F31,
+	EXYNOS4X12_GPIO_F32,
+	EXYNOS4X12_GPIO_F33,
+	EXYNOS4X12_GPIO_F34,
+	EXYNOS4X12_GPIO_F35,
+	EXYNOS4X12_GPIO_F36,
+	EXYNOS4X12_GPIO_F37,
+	EXYNOS4X12_GPIO_J00 = 144,	/* 144 0x90 */
+	EXYNOS4X12_GPIO_J01,
+	EXYNOS4X12_GPIO_J02,
+	EXYNOS4X12_GPIO_J03,
+	EXYNOS4X12_GPIO_J04,
+	EXYNOS4X12_GPIO_J05,
+	EXYNOS4X12_GPIO_J06,
+	EXYNOS4X12_GPIO_J07,
+	EXYNOS4X12_GPIO_J10,		/* 152 0x98 */
+	EXYNOS4X12_GPIO_J11,
+	EXYNOS4X12_GPIO_J12,
+	EXYNOS4X12_GPIO_J13,
+	EXYNOS4X12_GPIO_J14,
+	EXYNOS4X12_GPIO_J15,
+	EXYNOS4X12_GPIO_J16,
+	EXYNOS4X12_GPIO_J17,
+
+	/* GPIO_PART2_STARTS */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */
+	EXYNOS4X12_GPIO_K00 = 176,	/* 176 0xB0 */
+	EXYNOS4X12_GPIO_K01,
+	EXYNOS4X12_GPIO_K02,
+	EXYNOS4X12_GPIO_K03,
+	EXYNOS4X12_GPIO_K04,
+	EXYNOS4X12_GPIO_K05,
+	EXYNOS4X12_GPIO_K06,
+	EXYNOS4X12_GPIO_K07,
+	EXYNOS4X12_GPIO_K10,		/* 184 0xB8 */
+	EXYNOS4X12_GPIO_K11,
+	EXYNOS4X12_GPIO_K12,
+	EXYNOS4X12_GPIO_K13,
+	EXYNOS4X12_GPIO_K14,
+	EXYNOS4X12_GPIO_K15,
+	EXYNOS4X12_GPIO_K16,
+	EXYNOS4X12_GPIO_K17,
+	EXYNOS4X12_GPIO_K20,		/* 192 0xC0 */
+	EXYNOS4X12_GPIO_K21,
+	EXYNOS4X12_GPIO_K22,
+	EXYNOS4X12_GPIO_K23,
+	EXYNOS4X12_GPIO_K24,
+	EXYNOS4X12_GPIO_K25,
+	EXYNOS4X12_GPIO_K26,
+	EXYNOS4X12_GPIO_K27,
+	EXYNOS4X12_GPIO_K30,		/* 200 0xC8 */
+	EXYNOS4X12_GPIO_K31,
+	EXYNOS4X12_GPIO_K32,
+	EXYNOS4X12_GPIO_K33,
+	EXYNOS4X12_GPIO_K34,
+	EXYNOS4X12_GPIO_K35,
+	EXYNOS4X12_GPIO_K36,
+	EXYNOS4X12_GPIO_K37,
+	EXYNOS4X12_GPIO_L00,		/* 208 0xD0 */
+	EXYNOS4X12_GPIO_L01,
+	EXYNOS4X12_GPIO_L02,
+	EXYNOS4X12_GPIO_L03,
+	EXYNOS4X12_GPIO_L04,
+	EXYNOS4X12_GPIO_L05,
+	EXYNOS4X12_GPIO_L06,
+	EXYNOS4X12_GPIO_L07,
+	EXYNOS4X12_GPIO_L10,		/* 216 0xD8 */
+	EXYNOS4X12_GPIO_L11,
+	EXYNOS4X12_GPIO_L12,
+	EXYNOS4X12_GPIO_L13,
+	EXYNOS4X12_GPIO_L14,
+	EXYNOS4X12_GPIO_L15,
+	EXYNOS4X12_GPIO_L16,
+	EXYNOS4X12_GPIO_L17,
+	EXYNOS4X12_GPIO_L20,		/* 224 0xE0 */
+	EXYNOS4X12_GPIO_L21,
+	EXYNOS4X12_GPIO_L22,
+	EXYNOS4X12_GPIO_L23,
+	EXYNOS4X12_GPIO_L24,
+	EXYNOS4X12_GPIO_L25,
+	EXYNOS4X12_GPIO_L26,
+	EXYNOS4X12_GPIO_L27,
+	EXYNOS4X12_GPIO_Y00,		/* 232 0xE8 */
+	EXYNOS4X12_GPIO_Y01,
+	EXYNOS4X12_GPIO_Y02,
+	EXYNOS4X12_GPIO_Y03,
+	EXYNOS4X12_GPIO_Y04,
+	EXYNOS4X12_GPIO_Y05,
+	EXYNOS4X12_GPIO_Y06,
+	EXYNOS4X12_GPIO_Y07,
+	EXYNOS4X12_GPIO_Y10,		/* 240 0xF0 */
+	EXYNOS4X12_GPIO_Y11,
+	EXYNOS4X12_GPIO_Y12,
+	EXYNOS4X12_GPIO_Y13,
+	EXYNOS4X12_GPIO_Y14,
+	EXYNOS4X12_GPIO_Y15,
+	EXYNOS4X12_GPIO_Y16,
+	EXYNOS4X12_GPIO_Y17,
+	EXYNOS4X12_GPIO_Y20,		/* 248 0xF8 */
+	EXYNOS4X12_GPIO_Y21,
+	EXYNOS4X12_GPIO_Y22,
+	EXYNOS4X12_GPIO_Y23,
+	EXYNOS4X12_GPIO_Y24,
+	EXYNOS4X12_GPIO_Y25,
+	EXYNOS4X12_GPIO_Y26,
+	EXYNOS4X12_GPIO_Y27,
+	EXYNOS4X12_GPIO_Y30,		/* 256 0x100 */
+	EXYNOS4X12_GPIO_Y31,
+	EXYNOS4X12_GPIO_Y32,
+	EXYNOS4X12_GPIO_Y33,
+	EXYNOS4X12_GPIO_Y34,
+	EXYNOS4X12_GPIO_Y35,
+	EXYNOS4X12_GPIO_Y36,
+	EXYNOS4X12_GPIO_Y37,
+	EXYNOS4X12_GPIO_Y40,		/* 264 0x108 */
+	EXYNOS4X12_GPIO_Y41,
+	EXYNOS4X12_GPIO_Y42,
+	EXYNOS4X12_GPIO_Y43,
+	EXYNOS4X12_GPIO_Y44,
+	EXYNOS4X12_GPIO_Y45,
+	EXYNOS4X12_GPIO_Y46,
+	EXYNOS4X12_GPIO_Y47,
+	EXYNOS4X12_GPIO_Y50,		/* 272 0x110 */
+	EXYNOS4X12_GPIO_Y51,
+	EXYNOS4X12_GPIO_Y52,
+	EXYNOS4X12_GPIO_Y53,
+	EXYNOS4X12_GPIO_Y54,
+	EXYNOS4X12_GPIO_Y55,
+	EXYNOS4X12_GPIO_Y56,
+	EXYNOS4X12_GPIO_Y57,
+	EXYNOS4X12_GPIO_Y60,		/* 280 0x118 */
+	EXYNOS4X12_GPIO_Y61,
+	EXYNOS4X12_GPIO_Y62,
+	EXYNOS4X12_GPIO_Y63,
+	EXYNOS4X12_GPIO_Y64,
+	EXYNOS4X12_GPIO_Y65,
+	EXYNOS4X12_GPIO_Y66,
+	EXYNOS4X12_GPIO_Y67,
+	EXYNOS4X12_GPIO_M00 = 312,	/* 312 0xF0 */
+	EXYNOS4X12_GPIO_M01,
+	EXYNOS4X12_GPIO_M02,
+	EXYNOS4X12_GPIO_M03,
+	EXYNOS4X12_GPIO_M04,
+	EXYNOS4X12_GPIO_M05,
+	EXYNOS4X12_GPIO_M06,
+	EXYNOS4X12_GPIO_M07,
+	EXYNOS4X12_GPIO_M10,		/* 320 0xF8 */
+	EXYNOS4X12_GPIO_M11,
+	EXYNOS4X12_GPIO_M12,
+	EXYNOS4X12_GPIO_M13,
+	EXYNOS4X12_GPIO_M14,
+	EXYNOS4X12_GPIO_M15,
+	EXYNOS4X12_GPIO_M16,
+	EXYNOS4X12_GPIO_M17,
+	EXYNOS4X12_GPIO_M20,		/* 328 0x100 */
+	EXYNOS4X12_GPIO_M21,
+	EXYNOS4X12_GPIO_M22,
+	EXYNOS4X12_GPIO_M23,
+	EXYNOS4X12_GPIO_M24,
+	EXYNOS4X12_GPIO_M25,
+	EXYNOS4X12_GPIO_M26,
+	EXYNOS4X12_GPIO_M27,
+	EXYNOS4X12_GPIO_M30,		/* 336 0x108 */
+	EXYNOS4X12_GPIO_M31,
+	EXYNOS4X12_GPIO_M32,
+	EXYNOS4X12_GPIO_M33,
+	EXYNOS4X12_GPIO_M34,
+	EXYNOS4X12_GPIO_M35,
+	EXYNOS4X12_GPIO_M36,
+	EXYNOS4X12_GPIO_M37,
+	EXYNOS4X12_GPIO_M40,		/* 344 0x110 */
+	EXYNOS4X12_GPIO_M41,
+	EXYNOS4X12_GPIO_M42,
+	EXYNOS4X12_GPIO_M43,
+	EXYNOS4X12_GPIO_M44,
+	EXYNOS4X12_GPIO_M45,
+	EXYNOS4X12_GPIO_M46,
+	EXYNOS4X12_GPIO_M47,
+	EXYNOS4X12_GPIO_X00 = 928,	/* 928 0x3A0 */
+	EXYNOS4X12_GPIO_X01,
+	EXYNOS4X12_GPIO_X02,
+	EXYNOS4X12_GPIO_X03,
+	EXYNOS4X12_GPIO_X04,
+	EXYNOS4X12_GPIO_X05,
+	EXYNOS4X12_GPIO_X06,
+	EXYNOS4X12_GPIO_X07,
+	EXYNOS4X12_GPIO_X10,		/* 936 0x3A8 */
+	EXYNOS4X12_GPIO_X11,
+	EXYNOS4X12_GPIO_X12,
+	EXYNOS4X12_GPIO_X13,
+	EXYNOS4X12_GPIO_X14,
+	EXYNOS4X12_GPIO_X15,
+	EXYNOS4X12_GPIO_X16,
+	EXYNOS4X12_GPIO_X17,
+	EXYNOS4X12_GPIO_X20,		/* 944 0x3B0 */
+	EXYNOS4X12_GPIO_X21,
+	EXYNOS4X12_GPIO_X22,
+	EXYNOS4X12_GPIO_X23,
+	EXYNOS4X12_GPIO_X24,
+	EXYNOS4X12_GPIO_X25,
+	EXYNOS4X12_GPIO_X26,
+	EXYNOS4X12_GPIO_X27,
+	EXYNOS4X12_GPIO_X30,		/* 952 0x3B8 */
+	EXYNOS4X12_GPIO_X31,
+	EXYNOS4X12_GPIO_X32,
+	EXYNOS4X12_GPIO_X33,
+	EXYNOS4X12_GPIO_X34,
+	EXYNOS4X12_GPIO_X35,
+	EXYNOS4X12_GPIO_X36,
+	EXYNOS4X12_GPIO_X37,
+
+	/* GPIO_PART3_STARTS */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */
+	EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+	EXYNOS4X12_GPIO_Z1,
+	EXYNOS4X12_GPIO_Z2,
+	EXYNOS4X12_GPIO_Z3,
+	EXYNOS4X12_GPIO_Z4,
+	EXYNOS4X12_GPIO_Z5,
+	EXYNOS4X12_GPIO_Z6,
+	EXYNOS4X12_GPIO_Z7,
+
+	/* GPIO_PART4_STARTS */
+	EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */
+	EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
+	EXYNOS4X12_GPIO_V01,
+	EXYNOS4X12_GPIO_V02,
+	EXYNOS4X12_GPIO_V03,
+	EXYNOS4X12_GPIO_V04,
+	EXYNOS4X12_GPIO_V05,
+	EXYNOS4X12_GPIO_V06,
+	EXYNOS4X12_GPIO_V07,
+	EXYNOS4X12_GPIO_V10,		/* 976 0x3D0 */
+	EXYNOS4X12_GPIO_V11,
+	EXYNOS4X12_GPIO_V12,
+	EXYNOS4X12_GPIO_V13,
+	EXYNOS4X12_GPIO_V14,
+	EXYNOS4X12_GPIO_V15,
+	EXYNOS4X12_GPIO_V16,
+	EXYNOS4X12_GPIO_V17,
+	EXYNOS4X12_GPIO_V20 = 992,	/* 992 0x3E0 */
+	EXYNOS4X12_GPIO_V21,
+	EXYNOS4X12_GPIO_V22,
+	EXYNOS4X12_GPIO_V23,
+	EXYNOS4X12_GPIO_V24,
+	EXYNOS4X12_GPIO_V25,
+	EXYNOS4X12_GPIO_V26,
+	EXYNOS4X12_GPIO_V27,
+	EXYNOS4X12_GPIO_V30 = 1000,	/* 1000 0x3E8 */
+	EXYNOS4X12_GPIO_V31,
+	EXYNOS4X12_GPIO_V32,
+	EXYNOS4X12_GPIO_V33,
+	EXYNOS4X12_GPIO_V34,
+	EXYNOS4X12_GPIO_V35,
+	EXYNOS4X12_GPIO_V36,
+	EXYNOS4X12_GPIO_V37,
+	EXYNOS4X12_GPIO_V40 = 1016,	/* 1016 0x3F8 */
+	EXYNOS4X12_GPIO_V41,
+	EXYNOS4X12_GPIO_V42,
+	EXYNOS4X12_GPIO_V43,
+	EXYNOS4X12_GPIO_V44,
+	EXYNOS4X12_GPIO_V45,
+	EXYNOS4X12_GPIO_V46,
+	EXYNOS4X12_GPIO_V47,
+
+	EXYNOS4X12_GPIO_MAX_PORT
 };
 
-struct exynos4x12_gpio_part3 {
-	struct s5p_gpio_bank z;
+enum exynos5_gpio_pin {
+	/* GPIO_PART1_STARTS */
+	EXYNOS5_GPIO_A00,		/* 0 */
+	EXYNOS5_GPIO_A01,
+	EXYNOS5_GPIO_A02,
+	EXYNOS5_GPIO_A03,
+	EXYNOS5_GPIO_A04,
+	EXYNOS5_GPIO_A05,
+	EXYNOS5_GPIO_A06,
+	EXYNOS5_GPIO_A07,
+	EXYNOS5_GPIO_A10,		/* 8 */
+	EXYNOS5_GPIO_A11,
+	EXYNOS5_GPIO_A12,
+	EXYNOS5_GPIO_A13,
+	EXYNOS5_GPIO_A14,
+	EXYNOS5_GPIO_A15,
+	EXYNOS5_GPIO_A16,
+	EXYNOS5_GPIO_A17,
+	EXYNOS5_GPIO_A20,		/* 16 0x10 */
+	EXYNOS5_GPIO_A21,
+	EXYNOS5_GPIO_A22,
+	EXYNOS5_GPIO_A23,
+	EXYNOS5_GPIO_A24,
+	EXYNOS5_GPIO_A25,
+	EXYNOS5_GPIO_A26,
+	EXYNOS5_GPIO_A27,
+	EXYNOS5_GPIO_B00,		/* 24 0x18 */
+	EXYNOS5_GPIO_B01,
+	EXYNOS5_GPIO_B02,
+	EXYNOS5_GPIO_B03,
+	EXYNOS5_GPIO_B04,
+	EXYNOS5_GPIO_B05,
+	EXYNOS5_GPIO_B06,
+	EXYNOS5_GPIO_B07,
+	EXYNOS5_GPIO_B10,		/* 32 0x20 */
+	EXYNOS5_GPIO_B11,
+	EXYNOS5_GPIO_B12,
+	EXYNOS5_GPIO_B13,
+	EXYNOS5_GPIO_B14,
+	EXYNOS5_GPIO_B15,
+	EXYNOS5_GPIO_B16,
+	EXYNOS5_GPIO_B17,
+	EXYNOS5_GPIO_B20,		/* 40 0x28 */
+	EXYNOS5_GPIO_B21,
+	EXYNOS5_GPIO_B22,
+	EXYNOS5_GPIO_B23,
+	EXYNOS5_GPIO_B24,
+	EXYNOS5_GPIO_B25,
+	EXYNOS5_GPIO_B26,
+	EXYNOS5_GPIO_B27,
+	EXYNOS5_GPIO_B30,		/* 48 0x39 */
+	EXYNOS5_GPIO_B31,
+	EXYNOS5_GPIO_B32,
+	EXYNOS5_GPIO_B33,
+	EXYNOS5_GPIO_B34,
+	EXYNOS5_GPIO_B35,
+	EXYNOS5_GPIO_B36,
+	EXYNOS5_GPIO_B37,
+	EXYNOS5_GPIO_C00,		/* 56 0x38 */
+	EXYNOS5_GPIO_C01,
+	EXYNOS5_GPIO_C02,
+	EXYNOS5_GPIO_C03,
+	EXYNOS5_GPIO_C04,
+	EXYNOS5_GPIO_C05,
+	EXYNOS5_GPIO_C06,
+	EXYNOS5_GPIO_C07,
+	EXYNOS5_GPIO_C10,		/* 64 0x40 */
+	EXYNOS5_GPIO_C11,
+	EXYNOS5_GPIO_C12,
+	EXYNOS5_GPIO_C13,
+	EXYNOS5_GPIO_C14,
+	EXYNOS5_GPIO_C15,
+	EXYNOS5_GPIO_C16,
+	EXYNOS5_GPIO_C17,
+	EXYNOS5_GPIO_C20,		/* 72 0x48 */
+	EXYNOS5_GPIO_C21,
+	EXYNOS5_GPIO_C22,
+	EXYNOS5_GPIO_C23,
+	EXYNOS5_GPIO_C24,
+	EXYNOS5_GPIO_C25,
+	EXYNOS5_GPIO_C26,
+	EXYNOS5_GPIO_C27,
+	EXYNOS5_GPIO_C30,		/* 80 0x50 */
+	EXYNOS5_GPIO_C31,
+	EXYNOS5_GPIO_C32,
+	EXYNOS5_GPIO_C33,
+	EXYNOS5_GPIO_C34,
+	EXYNOS5_GPIO_C35,
+	EXYNOS5_GPIO_C36,
+	EXYNOS5_GPIO_C37,
+	EXYNOS5_GPIO_D00,		/* 88 0x58 */
+	EXYNOS5_GPIO_D01,
+	EXYNOS5_GPIO_D02,
+	EXYNOS5_GPIO_D03,
+	EXYNOS5_GPIO_D04,
+	EXYNOS5_GPIO_D05,
+	EXYNOS5_GPIO_D06,
+	EXYNOS5_GPIO_D07,
+	EXYNOS5_GPIO_D10,		/* 96 0x60 */
+	EXYNOS5_GPIO_D11,
+	EXYNOS5_GPIO_D12,
+	EXYNOS5_GPIO_D13,
+	EXYNOS5_GPIO_D14,
+	EXYNOS5_GPIO_D15,
+	EXYNOS5_GPIO_D16,
+	EXYNOS5_GPIO_D17,
+	EXYNOS5_GPIO_Y00,		/* 104 0x68 */
+	EXYNOS5_GPIO_Y01,
+	EXYNOS5_GPIO_Y02,
+	EXYNOS5_GPIO_Y03,
+	EXYNOS5_GPIO_Y04,
+	EXYNOS5_GPIO_Y05,
+	EXYNOS5_GPIO_Y06,
+	EXYNOS5_GPIO_Y07,
+	EXYNOS5_GPIO_Y10,		/* 112 0x70 */
+	EXYNOS5_GPIO_Y11,
+	EXYNOS5_GPIO_Y12,
+	EXYNOS5_GPIO_Y13,
+	EXYNOS5_GPIO_Y14,
+	EXYNOS5_GPIO_Y15,
+	EXYNOS5_GPIO_Y16,
+	EXYNOS5_GPIO_Y17,
+	EXYNOS5_GPIO_Y20,		/* 120 0x78 */
+	EXYNOS5_GPIO_Y21,
+	EXYNOS5_GPIO_Y22,
+	EXYNOS5_GPIO_Y23,
+	EXYNOS5_GPIO_Y24,
+	EXYNOS5_GPIO_Y25,
+	EXYNOS5_GPIO_Y26,
+	EXYNOS5_GPIO_Y27,
+	EXYNOS5_GPIO_Y30,		/* 128 0x80 */
+	EXYNOS5_GPIO_Y31,
+	EXYNOS5_GPIO_Y32,
+	EXYNOS5_GPIO_Y33,
+	EXYNOS5_GPIO_Y34,
+	EXYNOS5_GPIO_Y35,
+	EXYNOS5_GPIO_Y36,
+	EXYNOS5_GPIO_Y37,
+	EXYNOS5_GPIO_Y40,		/* 136 0x88 */
+	EXYNOS5_GPIO_Y41,
+	EXYNOS5_GPIO_Y42,
+	EXYNOS5_GPIO_Y43,
+	EXYNOS5_GPIO_Y44,
+	EXYNOS5_GPIO_Y45,
+	EXYNOS5_GPIO_Y46,
+	EXYNOS5_GPIO_Y47,
+	EXYNOS5_GPIO_Y50,		/* 144 0x90 */
+	EXYNOS5_GPIO_Y51,
+	EXYNOS5_GPIO_Y52,
+	EXYNOS5_GPIO_Y53,
+	EXYNOS5_GPIO_Y54,
+	EXYNOS5_GPIO_Y55,
+	EXYNOS5_GPIO_Y56,
+	EXYNOS5_GPIO_Y57,
+	EXYNOS5_GPIO_Y60,		/* 152 0x98 */
+	EXYNOS5_GPIO_Y61,
+	EXYNOS5_GPIO_Y62,
+	EXYNOS5_GPIO_Y63,
+	EXYNOS5_GPIO_Y64,
+	EXYNOS5_GPIO_Y65,
+	EXYNOS5_GPIO_Y66,
+	EXYNOS5_GPIO_Y67,
+
+	/* GPIO_PART2_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_1,	/* 160 0xa0 */
+	EXYNOS5_GPIO_C40 = EXYNOS5_GPIO_MAX_PORT_PART_1,
+	EXYNOS5_GPIO_C41,
+	EXYNOS5_GPIO_C42,
+	EXYNOS5_GPIO_C43,
+	EXYNOS5_GPIO_C44,
+	EXYNOS5_GPIO_C45,
+	EXYNOS5_GPIO_C46,
+	EXYNOS5_GPIO_C47,
+
+	/* GPIO_PART3_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_2,	/* 168 0xa8 */
+	EXYNOS5_GPIO_X00 = EXYNOS5_GPIO_MAX_PORT_PART_2,
+	EXYNOS5_GPIO_X01,
+	EXYNOS5_GPIO_X02,
+	EXYNOS5_GPIO_X03,
+	EXYNOS5_GPIO_X04,
+	EXYNOS5_GPIO_X05,
+	EXYNOS5_GPIO_X06,
+	EXYNOS5_GPIO_X07,
+	EXYNOS5_GPIO_X10,		/* 176 0xb0 */
+	EXYNOS5_GPIO_X11,
+	EXYNOS5_GPIO_X12,
+	EXYNOS5_GPIO_X13,
+	EXYNOS5_GPIO_X14,
+	EXYNOS5_GPIO_X15,
+	EXYNOS5_GPIO_X16,
+	EXYNOS5_GPIO_X17,
+	EXYNOS5_GPIO_X20,		/* 184 0xb8 */
+	EXYNOS5_GPIO_X21,
+	EXYNOS5_GPIO_X22,
+	EXYNOS5_GPIO_X23,
+	EXYNOS5_GPIO_X24,
+	EXYNOS5_GPIO_X25,
+	EXYNOS5_GPIO_X26,
+	EXYNOS5_GPIO_X27,
+	EXYNOS5_GPIO_X30,		/* 192 0xc0 */
+	EXYNOS5_GPIO_X31,
+	EXYNOS5_GPIO_X32,
+	EXYNOS5_GPIO_X33,
+	EXYNOS5_GPIO_X34,
+	EXYNOS5_GPIO_X35,
+	EXYNOS5_GPIO_X36,
+	EXYNOS5_GPIO_X37,
+
+	/* GPIO_PART4_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_3,	/* 200 0xc8 */
+	EXYNOS5_GPIO_E00 = EXYNOS5_GPIO_MAX_PORT_PART_3,
+	EXYNOS5_GPIO_E01,
+	EXYNOS5_GPIO_E02,
+	EXYNOS5_GPIO_E03,
+	EXYNOS5_GPIO_E04,
+	EXYNOS5_GPIO_E05,
+	EXYNOS5_GPIO_E06,
+	EXYNOS5_GPIO_E07,
+	EXYNOS5_GPIO_E10,		/* 208 0xd0 */
+	EXYNOS5_GPIO_E11,
+	EXYNOS5_GPIO_E12,
+	EXYNOS5_GPIO_E13,
+	EXYNOS5_GPIO_E14,
+	EXYNOS5_GPIO_E15,
+	EXYNOS5_GPIO_E16,
+	EXYNOS5_GPIO_E17,
+	EXYNOS5_GPIO_F00,		/* 216 0xd8 */
+	EXYNOS5_GPIO_F01,
+	EXYNOS5_GPIO_F02,
+	EXYNOS5_GPIO_F03,
+	EXYNOS5_GPIO_F04,
+	EXYNOS5_GPIO_F05,
+	EXYNOS5_GPIO_F06,
+	EXYNOS5_GPIO_F07,
+	EXYNOS5_GPIO_F10,		/* 224 0xe0 */
+	EXYNOS5_GPIO_F11,
+	EXYNOS5_GPIO_F12,
+	EXYNOS5_GPIO_F13,
+	EXYNOS5_GPIO_F14,
+	EXYNOS5_GPIO_F15,
+	EXYNOS5_GPIO_F16,
+	EXYNOS5_GPIO_F17,
+	EXYNOS5_GPIO_G00,		/* 232 0xe8 */
+	EXYNOS5_GPIO_G01,
+	EXYNOS5_GPIO_G02,
+	EXYNOS5_GPIO_G03,
+	EXYNOS5_GPIO_G04,
+	EXYNOS5_GPIO_G05,
+	EXYNOS5_GPIO_G06,
+	EXYNOS5_GPIO_G07,
+	EXYNOS5_GPIO_G10,		/* 240 0xf0 */
+	EXYNOS5_GPIO_G11,
+	EXYNOS5_GPIO_G12,
+	EXYNOS5_GPIO_G13,
+	EXYNOS5_GPIO_G14,
+	EXYNOS5_GPIO_G15,
+	EXYNOS5_GPIO_G16,
+	EXYNOS5_GPIO_G17,
+	EXYNOS5_GPIO_G20,		/* 248 0xf8 */
+	EXYNOS5_GPIO_G21,
+	EXYNOS5_GPIO_G22,
+	EXYNOS5_GPIO_G23,
+	EXYNOS5_GPIO_G24,
+	EXYNOS5_GPIO_G25,
+	EXYNOS5_GPIO_G26,
+	EXYNOS5_GPIO_G27,
+	EXYNOS5_GPIO_H00,		/* 256 0x100 */
+	EXYNOS5_GPIO_H01,
+	EXYNOS5_GPIO_H02,
+	EXYNOS5_GPIO_H03,
+	EXYNOS5_GPIO_H04,
+	EXYNOS5_GPIO_H05,
+	EXYNOS5_GPIO_H06,
+	EXYNOS5_GPIO_H07,
+	EXYNOS5_GPIO_H10,		/* 264 0x108 */
+	EXYNOS5_GPIO_H11,
+	EXYNOS5_GPIO_H12,
+	EXYNOS5_GPIO_H13,
+	EXYNOS5_GPIO_H14,
+	EXYNOS5_GPIO_H15,
+	EXYNOS5_GPIO_H16,
+	EXYNOS5_GPIO_H17,
+
+	/* GPIO_PART4_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_4,	/* 272 0x110 */
+	EXYNOS5_GPIO_V00 = EXYNOS5_GPIO_MAX_PORT_PART_4,
+	EXYNOS5_GPIO_V01,
+	EXYNOS5_GPIO_V02,
+	EXYNOS5_GPIO_V03,
+	EXYNOS5_GPIO_V04,
+	EXYNOS5_GPIO_V05,
+	EXYNOS5_GPIO_V06,
+	EXYNOS5_GPIO_V07,
+	EXYNOS5_GPIO_V10,		/* 280 0x118 */
+	EXYNOS5_GPIO_V11,
+	EXYNOS5_GPIO_V12,
+	EXYNOS5_GPIO_V13,
+	EXYNOS5_GPIO_V14,
+	EXYNOS5_GPIO_V15,
+	EXYNOS5_GPIO_V16,
+	EXYNOS5_GPIO_V17,
+
+	/* GPIO_PART5_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_5,	/* 288 0x120 */
+	EXYNOS5_GPIO_V20 = EXYNOS5_GPIO_MAX_PORT_PART_5,
+	EXYNOS5_GPIO_V21,
+	EXYNOS5_GPIO_V22,
+	EXYNOS5_GPIO_V23,
+	EXYNOS5_GPIO_V24,
+	EXYNOS5_GPIO_V25,
+	EXYNOS5_GPIO_V26,
+	EXYNOS5_GPIO_V27,
+	EXYNOS5_GPIO_V30,		/* 296 0x128 */
+	EXYNOS5_GPIO_V31,
+	EXYNOS5_GPIO_V32,
+	EXYNOS5_GPIO_V33,
+	EXYNOS5_GPIO_V34,
+	EXYNOS5_GPIO_V35,
+	EXYNOS5_GPIO_V36,
+	EXYNOS5_GPIO_V37,
+
+	/* GPIO_PART6_STARTS */
+	EXYNOS5_GPIO_MAX_PORT_PART_6,	/* 304 0x130 */
+	EXYNOS5_GPIO_V40 = EXYNOS5_GPIO_MAX_PORT_PART_6,
+	EXYNOS5_GPIO_V41,
+	EXYNOS5_GPIO_V42,
+	EXYNOS5_GPIO_V43,
+	EXYNOS5_GPIO_V44,
+	EXYNOS5_GPIO_V45,
+	EXYNOS5_GPIO_V46,
+	EXYNOS5_GPIO_V47,
+
+	/* GPIO_PART7_STARTS */		/* 312 0x138 */
+	EXYNOS5_GPIO_MAX_PORT_PART_7,
+	EXYNOS5_GPIO_Z0 = EXYNOS5_GPIO_MAX_PORT_PART_7,
+	EXYNOS5_GPIO_Z1,
+	EXYNOS5_GPIO_Z2,
+	EXYNOS5_GPIO_Z3,
+	EXYNOS5_GPIO_Z4,
+	EXYNOS5_GPIO_Z5,
+	EXYNOS5_GPIO_Z6,
+	EXYNOS5_GPIO_MAX_PORT
 };
 
-struct exynos4x12_gpio_part4 {
-	struct s5p_gpio_bank v0;
-	struct s5p_gpio_bank v1;
-	struct s5p_gpio_bank res1[0x1];
-	struct s5p_gpio_bank v2;
-	struct s5p_gpio_bank v3;
-	struct s5p_gpio_bank res2[0x1];
-	struct s5p_gpio_bank v4;
+enum exynos5420_gpio_pin {
+	/* GPIO_PART1_STARTS */
+	EXYNOS5420_GPIO_A00,		/* 0 */
+	EXYNOS5420_GPIO_A01,
+	EXYNOS5420_GPIO_A02,
+	EXYNOS5420_GPIO_A03,
+	EXYNOS5420_GPIO_A04,
+	EXYNOS5420_GPIO_A05,
+	EXYNOS5420_GPIO_A06,
+	EXYNOS5420_GPIO_A07,
+	EXYNOS5420_GPIO_A10,		/* 8 */
+	EXYNOS5420_GPIO_A11,
+	EXYNOS5420_GPIO_A12,
+	EXYNOS5420_GPIO_A13,
+	EXYNOS5420_GPIO_A14,
+	EXYNOS5420_GPIO_A15,
+	EXYNOS5420_GPIO_A16,
+	EXYNOS5420_GPIO_A17,
+	EXYNOS5420_GPIO_A20,		/* 16 0x10 */
+	EXYNOS5420_GPIO_A21,
+	EXYNOS5420_GPIO_A22,
+	EXYNOS5420_GPIO_A23,
+	EXYNOS5420_GPIO_A24,
+	EXYNOS5420_GPIO_A25,
+	EXYNOS5420_GPIO_A26,
+	EXYNOS5420_GPIO_A27,
+	EXYNOS5420_GPIO_B00,		/* 24 0x18 */
+	EXYNOS5420_GPIO_B01,
+	EXYNOS5420_GPIO_B02,
+	EXYNOS5420_GPIO_B03,
+	EXYNOS5420_GPIO_B04,
+	EXYNOS5420_GPIO_B05,
+	EXYNOS5420_GPIO_B06,
+	EXYNOS5420_GPIO_B07,
+	EXYNOS5420_GPIO_B10,		/* 32 0x20 */
+	EXYNOS5420_GPIO_B11,
+	EXYNOS5420_GPIO_B12,
+	EXYNOS5420_GPIO_B13,
+	EXYNOS5420_GPIO_B14,
+	EXYNOS5420_GPIO_B15,
+	EXYNOS5420_GPIO_B16,
+	EXYNOS5420_GPIO_B17,
+	EXYNOS5420_GPIO_B20,		/* 40 0x28 */
+	EXYNOS5420_GPIO_B21,
+	EXYNOS5420_GPIO_B22,
+	EXYNOS5420_GPIO_B23,
+	EXYNOS5420_GPIO_B24,
+	EXYNOS5420_GPIO_B25,
+	EXYNOS5420_GPIO_B26,
+	EXYNOS5420_GPIO_B27,
+	EXYNOS5420_GPIO_B30,		/* 48 0x30 */
+	EXYNOS5420_GPIO_B31,
+	EXYNOS5420_GPIO_B32,
+	EXYNOS5420_GPIO_B33,
+	EXYNOS5420_GPIO_B34,
+	EXYNOS5420_GPIO_B35,
+	EXYNOS5420_GPIO_B36,
+	EXYNOS5420_GPIO_B37,
+	EXYNOS5420_GPIO_B40,		/* 56 0x38 */
+	EXYNOS5420_GPIO_B41,
+	EXYNOS5420_GPIO_B42,
+	EXYNOS5420_GPIO_B43,
+	EXYNOS5420_GPIO_B44,
+	EXYNOS5420_GPIO_B45,
+	EXYNOS5420_GPIO_B46,
+	EXYNOS5420_GPIO_B47,
+	EXYNOS5420_GPIO_H00,		/* 64 0x40 */
+	EXYNOS5420_GPIO_H01,
+	EXYNOS5420_GPIO_H02,
+	EXYNOS5420_GPIO_H03,
+	EXYNOS5420_GPIO_H04,
+	EXYNOS5420_GPIO_H05,
+	EXYNOS5420_GPIO_H06,
+	EXYNOS5420_GPIO_H07,
+
+	/* GPIO PART 2 STARTS*/
+	EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
+	EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+	EXYNOS5420_GPIO_Y71,
+	EXYNOS5420_GPIO_Y72,
+	EXYNOS5420_GPIO_Y73,
+	EXYNOS5420_GPIO_Y74,
+	EXYNOS5420_GPIO_Y75,
+	EXYNOS5420_GPIO_Y76,
+	EXYNOS5420_GPIO_Y77,
+
+	/* GPIO PART 3 STARTS*/
+	EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
+	EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+	EXYNOS5420_GPIO_X01,
+	EXYNOS5420_GPIO_X02,
+	EXYNOS5420_GPIO_X03,
+	EXYNOS5420_GPIO_X04,
+	EXYNOS5420_GPIO_X05,
+	EXYNOS5420_GPIO_X06,
+	EXYNOS5420_GPIO_X07,
+	EXYNOS5420_GPIO_X10,		/* 88 0x58 */
+	EXYNOS5420_GPIO_X11,
+	EXYNOS5420_GPIO_X12,
+	EXYNOS5420_GPIO_X13,
+	EXYNOS5420_GPIO_X14,
+	EXYNOS5420_GPIO_X15,
+	EXYNOS5420_GPIO_X16,
+	EXYNOS5420_GPIO_X17,
+	EXYNOS5420_GPIO_X20,		/* 96 0x60 */
+	EXYNOS5420_GPIO_X21,
+	EXYNOS5420_GPIO_X22,
+	EXYNOS5420_GPIO_X23,
+	EXYNOS5420_GPIO_X24,
+	EXYNOS5420_GPIO_X25,
+	EXYNOS5420_GPIO_X26,
+	EXYNOS5420_GPIO_X27,
+	EXYNOS5420_GPIO_X30,		/* 104 0x68 */
+	EXYNOS5420_GPIO_X31,
+	EXYNOS5420_GPIO_X32,
+	EXYNOS5420_GPIO_X33,
+	EXYNOS5420_GPIO_X34,
+	EXYNOS5420_GPIO_X35,
+	EXYNOS5420_GPIO_X36,
+	EXYNOS5420_GPIO_X37,
+
+	/* GPIO PART 4 STARTS*/
+	EXYNOS5420_GPIO_MAX_PORT_PART_3,/* 112 0x70 */
+	EXYNOS5420_GPIO_C00 = EXYNOS5420_GPIO_MAX_PORT_PART_3,
+	EXYNOS5420_GPIO_C01,
+	EXYNOS5420_GPIO_C02,
+	EXYNOS5420_GPIO_C03,
+	EXYNOS5420_GPIO_C04,
+	EXYNOS5420_GPIO_C05,
+	EXYNOS5420_GPIO_C06,
+	EXYNOS5420_GPIO_C07,
+	EXYNOS5420_GPIO_C10,		/* 120 0x78 */
+	EXYNOS5420_GPIO_C11,
+	EXYNOS5420_GPIO_C12,
+	EXYNOS5420_GPIO_C13,
+	EXYNOS5420_GPIO_C14,
+	EXYNOS5420_GPIO_C15,
+	EXYNOS5420_GPIO_C16,
+	EXYNOS5420_GPIO_C17,
+	EXYNOS5420_GPIO_C20,		/* 128 0x80 */
+	EXYNOS5420_GPIO_C21,
+	EXYNOS5420_GPIO_C22,
+	EXYNOS5420_GPIO_C23,
+	EXYNOS5420_GPIO_C24,
+	EXYNOS5420_GPIO_C25,
+	EXYNOS5420_GPIO_C26,
+	EXYNOS5420_GPIO_C27,
+	EXYNOS5420_GPIO_C30,		/* 136 0x88 */
+	EXYNOS5420_GPIO_C31,
+	EXYNOS5420_GPIO_C32,
+	EXYNOS5420_GPIO_C33,
+	EXYNOS5420_GPIO_C34,
+	EXYNOS5420_GPIO_C35,
+	EXYNOS5420_GPIO_C36,
+	EXYNOS5420_GPIO_C37,
+	EXYNOS5420_GPIO_C40,		/* 144 0x90 */
+	EXYNOS5420_GPIO_C41,
+	EXYNOS5420_GPIO_C42,
+	EXYNOS5420_GPIO_C43,
+	EXYNOS5420_GPIO_C44,
+	EXYNOS5420_GPIO_C45,
+	EXYNOS5420_GPIO_C46,
+	EXYNOS5420_GPIO_C47,
+	EXYNOS5420_GPIO_D10,		/* 152 0x98 */
+	EXYNOS5420_GPIO_D11,
+	EXYNOS5420_GPIO_D12,
+	EXYNOS5420_GPIO_D13,
+	EXYNOS5420_GPIO_D14,
+	EXYNOS5420_GPIO_D15,
+	EXYNOS5420_GPIO_D16,
+	EXYNOS5420_GPIO_D17,
+	EXYNOS5420_GPIO_Y00,		/* 160 0xa0 */
+	EXYNOS5420_GPIO_Y01,
+	EXYNOS5420_GPIO_Y02,
+	EXYNOS5420_GPIO_Y03,
+	EXYNOS5420_GPIO_Y04,
+	EXYNOS5420_GPIO_Y05,
+	EXYNOS5420_GPIO_Y06,
+	EXYNOS5420_GPIO_Y07,
+	EXYNOS5420_GPIO_Y10,		/* 168 0xa8 */
+	EXYNOS5420_GPIO_Y11,
+	EXYNOS5420_GPIO_Y12,
+	EXYNOS5420_GPIO_Y13,
+	EXYNOS5420_GPIO_Y14,
+	EXYNOS5420_GPIO_Y15,
+	EXYNOS5420_GPIO_Y16,
+	EXYNOS5420_GPIO_Y17,
+	EXYNOS5420_GPIO_Y20,		/* 176 0xb0 */
+	EXYNOS5420_GPIO_Y21,
+	EXYNOS5420_GPIO_Y22,
+	EXYNOS5420_GPIO_Y23,
+	EXYNOS5420_GPIO_Y24,
+	EXYNOS5420_GPIO_Y25,
+	EXYNOS5420_GPIO_Y26,
+	EXYNOS5420_GPIO_Y27,
+	EXYNOS5420_GPIO_Y30,		/* 184 0xb8 */
+	EXYNOS5420_GPIO_Y31,
+	EXYNOS5420_GPIO_Y32,
+	EXYNOS5420_GPIO_Y33,
+	EXYNOS5420_GPIO_Y34,
+	EXYNOS5420_GPIO_Y35,
+	EXYNOS5420_GPIO_Y36,
+	EXYNOS5420_GPIO_Y37,
+	EXYNOS5420_GPIO_Y40,		/* 192 0xc0 */
+	EXYNOS5420_GPIO_Y41,
+	EXYNOS5420_GPIO_Y42,
+	EXYNOS5420_GPIO_Y43,
+	EXYNOS5420_GPIO_Y44,
+	EXYNOS5420_GPIO_Y45,
+	EXYNOS5420_GPIO_Y46,
+	EXYNOS5420_GPIO_Y47,
+	EXYNOS5420_GPIO_Y50,		/* 200 0xc8 */
+	EXYNOS5420_GPIO_Y51,
+	EXYNOS5420_GPIO_Y52,
+	EXYNOS5420_GPIO_Y53,
+	EXYNOS5420_GPIO_Y54,
+	EXYNOS5420_GPIO_Y55,
+	EXYNOS5420_GPIO_Y56,
+	EXYNOS5420_GPIO_Y57,
+	EXYNOS5420_GPIO_Y60,		/* 208 0xd0 */
+	EXYNOS5420_GPIO_Y61,
+	EXYNOS5420_GPIO_Y62,
+	EXYNOS5420_GPIO_Y63,
+	EXYNOS5420_GPIO_Y64,
+	EXYNOS5420_GPIO_Y65,
+	EXYNOS5420_GPIO_Y66,
+	EXYNOS5420_GPIO_Y67,
+
+	/* GPIO_PART5_STARTS */
+	EXYNOS5420_GPIO_MAX_PORT_PART_4,/* 216 0xd8 */
+	EXYNOS5420_GPIO_E00 = EXYNOS5420_GPIO_MAX_PORT_PART_4,
+	EXYNOS5420_GPIO_E01,
+	EXYNOS5420_GPIO_E02,
+	EXYNOS5420_GPIO_E03,
+	EXYNOS5420_GPIO_E04,
+	EXYNOS5420_GPIO_E05,
+	EXYNOS5420_GPIO_E06,
+	EXYNOS5420_GPIO_E07,
+	EXYNOS5420_GPIO_E10,		/* 224 0xe0 */
+	EXYNOS5420_GPIO_E11,
+	EXYNOS5420_GPIO_E12,
+	EXYNOS5420_GPIO_E13,
+	EXYNOS5420_GPIO_E14,
+	EXYNOS5420_GPIO_E15,
+	EXYNOS5420_GPIO_E16,
+	EXYNOS5420_GPIO_E17,
+	EXYNOS5420_GPIO_F00,		/* 232 0xe8 */
+	EXYNOS5420_GPIO_F01,
+	EXYNOS5420_GPIO_F02,
+	EXYNOS5420_GPIO_F03,
+	EXYNOS5420_GPIO_F04,
+	EXYNOS5420_GPIO_F05,
+	EXYNOS5420_GPIO_F06,
+	EXYNOS5420_GPIO_F07,
+	EXYNOS5420_GPIO_F10,		/* 240 0xf0 */
+	EXYNOS5420_GPIO_F11,
+	EXYNOS5420_GPIO_F12,
+	EXYNOS5420_GPIO_F13,
+	EXYNOS5420_GPIO_F14,
+	EXYNOS5420_GPIO_F15,
+	EXYNOS5420_GPIO_F16,
+	EXYNOS5420_GPIO_F17,
+	EXYNOS5420_GPIO_G00,		/* 248 0xf8 */
+	EXYNOS5420_GPIO_G01,
+	EXYNOS5420_GPIO_G02,
+	EXYNOS5420_GPIO_G03,
+	EXYNOS5420_GPIO_G04,
+	EXYNOS5420_GPIO_G05,
+	EXYNOS5420_GPIO_G06,
+	EXYNOS5420_GPIO_G07,
+	EXYNOS5420_GPIO_G10,		/* 256 0x100 */
+	EXYNOS5420_GPIO_G11,
+	EXYNOS5420_GPIO_G12,
+	EXYNOS5420_GPIO_G13,
+	EXYNOS5420_GPIO_G14,
+	EXYNOS5420_GPIO_G15,
+	EXYNOS5420_GPIO_G16,
+	EXYNOS5420_GPIO_G17,
+	EXYNOS5420_GPIO_G20,		/* 264 0x108 */
+	EXYNOS5420_GPIO_G21,
+	EXYNOS5420_GPIO_G22,
+	EXYNOS5420_GPIO_G23,
+	EXYNOS5420_GPIO_G24,
+	EXYNOS5420_GPIO_G25,
+	EXYNOS5420_GPIO_G26,
+	EXYNOS5420_GPIO_G27,
+	EXYNOS5420_GPIO_J40,		/* 272 0x110 */
+	EXYNOS5420_GPIO_J41,
+	EXYNOS5420_GPIO_J42,
+	EXYNOS5420_GPIO_J43,
+	EXYNOS5420_GPIO_J44,
+	EXYNOS5420_GPIO_J45,
+	EXYNOS5420_GPIO_J46,
+	EXYNOS5420_GPIO_J47,
+
+	/* GPIO_PART6_STARTS */
+	EXYNOS5420_GPIO_MAX_PORT_PART_5,/* 280 0x118 */
+	EXYNOS5420_GPIO_Z0 = EXYNOS5420_GPIO_MAX_PORT_PART_5,
+	EXYNOS5420_GPIO_Z1,
+	EXYNOS5420_GPIO_Z2,
+	EXYNOS5420_GPIO_Z3,
+	EXYNOS5420_GPIO_Z4,
+	EXYNOS5420_GPIO_Z5,
+	EXYNOS5420_GPIO_Z6,
+	EXYNOS5420_GPIO_MAX_PORT
 };
 
-struct exynos5420_gpio_part1 {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank a2;
-	struct s5p_gpio_bank b0;
-	struct s5p_gpio_bank b1;
-	struct s5p_gpio_bank b2;
-	struct s5p_gpio_bank b3;
-	struct s5p_gpio_bank b4;
-	struct s5p_gpio_bank h0;
+struct gpio_info {
+	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned int max_gpio;	/* Maximum GPIO in this part */
 };
 
-struct exynos5420_gpio_part2 {
-	struct s5p_gpio_bank y7; /* 0x1340_0000 */
-	struct s5p_gpio_bank res[0x5f]; /*  */
-	struct s5p_gpio_bank x0; /* 0x1340_0C00 */
-	struct s5p_gpio_bank x1; /* 0x1340_0C20 */
-	struct s5p_gpio_bank x2; /* 0x1340_0C40 */
-	struct s5p_gpio_bank x3; /* 0x1340_0C60 */
+#define EXYNOS4_GPIO_NUM_PARTS	3
+static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
+	{ EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
 };
 
-struct exynos5420_gpio_part3 {
-	struct s5p_gpio_bank c0;
-	struct s5p_gpio_bank c1;
-	struct s5p_gpio_bank c2;
-	struct s5p_gpio_bank c3;
-	struct s5p_gpio_bank c4;
-	struct s5p_gpio_bank d1;
-	struct s5p_gpio_bank y0;
-	struct s5p_gpio_bank y1;
-	struct s5p_gpio_bank y2;
-	struct s5p_gpio_bank y3;
-	struct s5p_gpio_bank y4;
-	struct s5p_gpio_bank y5;
-	struct s5p_gpio_bank y6;
+#define EXYNOS4X12_GPIO_NUM_PARTS	4
+static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
+	{ EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
 };
 
-struct exynos5420_gpio_part4 {
-	struct s5p_gpio_bank e0; /* 0x1400_0000 */
-	struct s5p_gpio_bank e1; /* 0x1400_0020 */
-	struct s5p_gpio_bank f0; /* 0x1400_0040 */
-	struct s5p_gpio_bank f1; /* 0x1400_0060 */
-	struct s5p_gpio_bank g0; /* 0x1400_0080 */
-	struct s5p_gpio_bank g1; /* 0x1400_00A0 */
-	struct s5p_gpio_bank g2; /* 0x1400_00C0 */
-	struct s5p_gpio_bank j4; /* 0x1400_00E0 */
+#define EXYNOS5_GPIO_NUM_PARTS	8
+static struct gpio_info exynos5_gpio_data[EXYNOS5_GPIO_NUM_PARTS] = {
+	{ EXYNOS5_GPIO_PART1_BASE, EXYNOS5_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS5_GPIO_PART2_BASE, EXYNOS5_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS5_GPIO_PART3_BASE, EXYNOS5_GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS5_GPIO_PART4_BASE, EXYNOS5_GPIO_MAX_PORT_PART_4 },
+	{ EXYNOS5_GPIO_PART5_BASE, EXYNOS5_GPIO_MAX_PORT_PART_5 },
+	{ EXYNOS5_GPIO_PART6_BASE, EXYNOS5_GPIO_MAX_PORT_PART_6 },
+	{ EXYNOS5_GPIO_PART7_BASE, EXYNOS5_GPIO_MAX_PORT_PART_7 },
+	{ EXYNOS5_GPIO_PART8_BASE, EXYNOS5_GPIO_MAX_PORT },
 };
 
-struct exynos5420_gpio_part5 {
-	struct s5p_gpio_bank z0; /* 0x0386_0000 */
+#define EXYNOS5420_GPIO_NUM_PARTS	6
+static struct gpio_info exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
+	{ EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+	{ EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_5 },
+	{ EXYNOS5420_GPIO_PART6_BASE, EXYNOS5420_GPIO_MAX_PORT },
 };
 
-struct exynos5_gpio_part1 {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank a2;
-	struct s5p_gpio_bank b0;
-	struct s5p_gpio_bank b1;
-	struct s5p_gpio_bank b2;
-	struct s5p_gpio_bank b3;
-	struct s5p_gpio_bank c0;
-	struct s5p_gpio_bank c1;
-	struct s5p_gpio_bank c2;
-	struct s5p_gpio_bank c3;
-	struct s5p_gpio_bank d0;
-	struct s5p_gpio_bank d1;
-	struct s5p_gpio_bank y0;
-	struct s5p_gpio_bank y1;
-	struct s5p_gpio_bank y2;
-	struct s5p_gpio_bank y3;
-	struct s5p_gpio_bank y4;
-	struct s5p_gpio_bank y5;
-	struct s5p_gpio_bank y6;
-	struct s5p_gpio_bank res1[0x3];
-	struct s5p_gpio_bank c4;
-	struct s5p_gpio_bank res2[0x48];
-	struct s5p_gpio_bank x0;
-	struct s5p_gpio_bank x1;
-	struct s5p_gpio_bank x2;
-	struct s5p_gpio_bank x3;
+static inline struct gpio_info *get_gpio_data(void)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return exynos5420_gpio_data;
+		else
+			return exynos5_gpio_data;
+	} else if (cpu_is_exynos4()) {
+		if (proid_is_exynos4412())
+			return exynos4x12_gpio_data;
+		else
+			return exynos4_gpio_data;
+	}
+
+	return NULL;
+}
+
+static inline unsigned int get_bank_num(void)
+{
+	if (cpu_is_exynos5()) {
+		if (proid_is_exynos5420())
+			return EXYNOS5420_GPIO_NUM_PARTS;
+		else
+			return EXYNOS5_GPIO_NUM_PARTS;
+	} else if (cpu_is_exynos4()) {
+		if (proid_is_exynos4412())
+			return EXYNOS4X12_GPIO_NUM_PARTS;
+		else
+			return EXYNOS4_GPIO_NUM_PARTS;
+	}
+
+	return 0;
+}
+
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ *   p is optional
+ *   <bank> - a single character bank name, as defined by the SOC
+ *   <set> - a single digit set number
+ *   <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+	char bank;		/* bank name symbol */
+	unsigned int bank_size;		/* total number of pins in the bank */
+	char bank_offset;	/* offset of the first bank's pin */
+	unsigned int base;	/* index of the first bank's pin in the enum */
 };
 
-struct exynos5_gpio_part2 {
-	struct s5p_gpio_bank e0;
-	struct s5p_gpio_bank e1;
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank g0;
-	struct s5p_gpio_bank g1;
-	struct s5p_gpio_bank g2;
-	struct s5p_gpio_bank h0;
-	struct s5p_gpio_bank h1;
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table exynos4_gpio_table[] = {
+	GPIO_ENTRY('a', EXYNOS4_GPIO_A00, EXYNOS4_GPIO_B0, 0),
+	GPIO_ENTRY('b', EXYNOS4_GPIO_B0, EXYNOS4_GPIO_C00, 0),
+	GPIO_ENTRY('c', EXYNOS4_GPIO_C00, EXYNOS4_GPIO_D00, 0),
+	GPIO_ENTRY('d', EXYNOS4_GPIO_D00, EXYNOS4_GPIO_E00, 0),
+	GPIO_ENTRY('e', EXYNOS4_GPIO_E00, EXYNOS4_GPIO_F00, 0),
+	GPIO_ENTRY('f', EXYNOS4_GPIO_F00, EXYNOS4_GPIO_J00, 0),
+	GPIO_ENTRY('j', EXYNOS4_GPIO_J00, EXYNOS4_GPIO_K00, 0),
+	GPIO_ENTRY('k', EXYNOS4_GPIO_K00, EXYNOS4_GPIO_L00, 0),
+	GPIO_ENTRY('l', EXYNOS4_GPIO_L00, EXYNOS4_GPIO_Y00, 0),
+	GPIO_ENTRY('y', EXYNOS4_GPIO_Y00, EXYNOS4_GPIO_X00, 0),
+	GPIO_ENTRY('x', EXYNOS4_GPIO_X00, EXYNOS4_GPIO_Z0, 0),
+	GPIO_ENTRY('z', EXYNOS4_GPIO_Z0, EXYNOS4_GPIO_MAX_PORT, 0),
+	{ 0 }
 };
 
-struct exynos5_gpio_part3 {
-	struct s5p_gpio_bank v0;
-	struct s5p_gpio_bank v1;
-	struct s5p_gpio_bank res1[0x1];
-	struct s5p_gpio_bank v2;
-	struct s5p_gpio_bank v3;
-	struct s5p_gpio_bank res2[0x1];
-	struct s5p_gpio_bank v4;
+static const struct gpio_name_num_table exynos4x12_gpio_table[] = {
+	GPIO_ENTRY('a', EXYNOS4X12_GPIO_A00, EXYNOS4X12_GPIO_B0, 0),
+	GPIO_ENTRY('b', EXYNOS4X12_GPIO_B0, EXYNOS4X12_GPIO_C00, 0),
+	GPIO_ENTRY('c', EXYNOS4X12_GPIO_C00, EXYNOS4X12_GPIO_D00, 0),
+	GPIO_ENTRY('d', EXYNOS4X12_GPIO_D00, EXYNOS4X12_GPIO_F00, 0),
+	GPIO_ENTRY('f', EXYNOS4X12_GPIO_F00, EXYNOS4X12_GPIO_J00, 0),
+	GPIO_ENTRY('j', EXYNOS4X12_GPIO_J00, EXYNOS4X12_GPIO_K00, 0),
+	GPIO_ENTRY('k', EXYNOS4X12_GPIO_K00, EXYNOS4X12_GPIO_L00, 0),
+	GPIO_ENTRY('l', EXYNOS4X12_GPIO_L00, EXYNOS4X12_GPIO_Y00, 0),
+	GPIO_ENTRY('y', EXYNOS4X12_GPIO_Y00, EXYNOS4X12_GPIO_M00, 0),
+	GPIO_ENTRY('m', EXYNOS4X12_GPIO_M00, EXYNOS4X12_GPIO_X00, 0),
+	GPIO_ENTRY('x', EXYNOS4X12_GPIO_X00, EXYNOS4X12_GPIO_Z0, 0),
+	GPIO_ENTRY('z', EXYNOS4X12_GPIO_Z0, EXYNOS4X12_GPIO_V00, 0),
+	GPIO_ENTRY('v', EXYNOS4X12_GPIO_V00, EXYNOS4X12_GPIO_MAX_PORT, 0),
+	{ 0 }
 };
 
-struct exynos5_gpio_part4 {
-	struct s5p_gpio_bank z;
+static const struct gpio_name_num_table exynos5_gpio_table[] = {
+	GPIO_ENTRY('a', EXYNOS5_GPIO_A00, EXYNOS5_GPIO_B00, 0),
+	GPIO_ENTRY('b', EXYNOS5_GPIO_B00, EXYNOS5_GPIO_C00, 0),
+	GPIO_ENTRY('c', EXYNOS5_GPIO_C00, EXYNOS5_GPIO_D00, 0),
+	GPIO_ENTRY('d', EXYNOS5_GPIO_D00, EXYNOS5_GPIO_Y00, 0),
+	GPIO_ENTRY('y', EXYNOS5_GPIO_Y00, EXYNOS5_GPIO_C40, 0),
+	GPIO_ENTRY('x', EXYNOS5_GPIO_X00, EXYNOS5_GPIO_E00, 0),
+	GPIO_ENTRY('e', EXYNOS5_GPIO_E00, EXYNOS5_GPIO_F00, 0),
+	GPIO_ENTRY('f', EXYNOS5_GPIO_F00, EXYNOS5_GPIO_G00, 0),
+	GPIO_ENTRY('g', EXYNOS5_GPIO_G00, EXYNOS5_GPIO_H00, 0),
+	GPIO_ENTRY('h', EXYNOS5_GPIO_H00, EXYNOS5_GPIO_V00, 0),
+	GPIO_ENTRY('v', EXYNOS5_GPIO_V00, EXYNOS5_GPIO_Z0, 0),
+	GPIO_ENTRY('z', EXYNOS5_GPIO_Z0, EXYNOS5_GPIO_MAX_PORT, 0),
+	{ 0 }
 };
 
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+static const struct gpio_name_num_table exynos5420_gpio_table[] = {
+	GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+	GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+	GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Y70, 0),
+	GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+	GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+	GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 010),
+	GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+	GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+	GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+	GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+	GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_Z0, 040),
+	GPIO_ENTRY('z', EXYNOS5420_GPIO_Z0, EXYNOS5420_GPIO_MAX_PORT, 0),
+	{ 0 }
+};
 
-/* GPIO pins per bank  */
-#define GPIO_PER_BANK 8
-#define S5P_GPIO_PART_SHIFT	(24)
-#define S5P_GPIO_PART_MASK	(0xff)
-#define S5P_GPIO_BANK_SHIFT	(8)
-#define S5P_GPIO_BANK_MASK	(0xffff)
-#define S5P_GPIO_PIN_MASK	(0xff)
-
-#define S5P_GPIO_SET_PART(x) \
-			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
-
-#define S5P_GPIO_GET_PART(x) \
-			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
-
-#define S5P_GPIO_SET_PIN(x) \
-			((x) & S5P_GPIO_PIN_MASK)
-
-#define EXYNOS4_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos4_gpio_part##part *) \
-			EXYNOS4_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS4_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos4x12_gpio_part##part *) \
-			EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS4X12_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS5_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
-			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS5_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define EXYNOS5420_GPIO_SET_BANK(part, bank) \
-			((((unsigned)&(((struct exynos5420_gpio_part##part *) \
-			EXYNOS5420_GPIO_PART##part##_BASE)->bank) \
-			- EXYNOS5420_GPIO_PART##part##_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
-
-#define exynos4_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS4_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-#define exynos4x12_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS4X12_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-#define exynos5420_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS5420_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-#define exynos5_gpio_get(part, bank, pin) \
-			(S5P_GPIO_SET_PART(part) | \
-			EXYNOS5_GPIO_SET_BANK(part, bank) | \
-			S5P_GPIO_SET_PIN(pin))
-
-static inline unsigned int s5p_gpio_base(int gpio)
-{
-	unsigned gpio_part = S5P_GPIO_GET_PART(gpio);
-
-	switch (gpio_part) {
-	case 1:
-		return samsung_get_base_gpio_part1();
-	case 2:
-		return samsung_get_base_gpio_part2();
-	case 3:
-		return samsung_get_base_gpio_part3();
-	case 4:
-		return samsung_get_base_gpio_part4();
-	default:
-		return 0;
-	}
-}
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_set_value(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_rate(int gpio, int mode);
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
+int s5p_gpio_get_pin(unsigned gpio);
 #endif
 
 /* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
+#define S5P_GPIO_INPUT	0x0
+#define S5P_GPIO_OUTPUT	0x1
+#define S5P_GPIO_IRQ	0xf
+#define S5P_GPIO_FUNC(x)	(x)
 
 /* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x3
+#define S5P_GPIO_PULL_NONE	0x0
+#define S5P_GPIO_PULL_DOWN	0x1
+#define S5P_GPIO_PULL_UP	0x3
 
 /* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_3X	0x1
-#define GPIO_DRV_2X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
+#define S5P_GPIO_DRV_1X	0x0
+#define S5P_GPIO_DRV_3X	0x1
+#define S5P_GPIO_DRV_2X	0x2
+#define S5P_GPIO_DRV_4X	0x3
+#define S5P_GPIO_DRV_FAST	0x0
+#define S5P_GPIO_DRV_SLOW	0x1
 #endif
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index a17f828..3dffa4a 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -161,6 +161,126 @@ struct aips_regs {
 	u32 mpr_0_7;
 	u32 mpr_8_15;
 };
+/* LCD controller registers */
+struct lcdc_regs {
+	u32 lssar;	/* Screen Start Address */
+	u32 lsr;	/* Size */
+	u32 lvpwr;	/* Virtual Page Width */
+	u32 lcpr;	/* Cursor Position */
+	u32 lcwhb;	/* Cursor Width Height and Blink */
+	u32 lccmr;	/* Color Cursor Mapping */
+	u32 lpcr;	/* Panel Configuration */
+	u32 lhcr;	/* Horizontal Configuration */
+	u32 lvcr;	/* Vertical Configuration */
+	u32 lpor;	/* Panning Offset */
+	u32 lscr;	/* Sharp Configuration */
+	u32 lpccr;	/* PWM Contrast Control */
+	u32 ldcr;	/* DMA Control */
+	u32 lrmcr;	/* Refresh Mode Control */
+	u32 licr;	/* Interrupt Configuration */
+	u32 lier;	/* Interrupt Enable */
+	u32 lisr;	/* Interrupt Status */
+	u32 res0[3];
+	u32 lgwsar;	/* Graphic Window Start Address */
+	u32 lgwsr;	/* Graphic Window Size */
+	u32 lgwvpwr;	/* Graphic Window Virtual Page Width Regist */
+	u32 lgwpor;	/* Graphic Window Panning Offset */
+	u32 lgwpr;	/* Graphic Window Position */
+	u32 lgwcr;	/* Graphic Window Control */
+	u32 lgwdcr;	/* Graphic Window DMA Control */
+	u32 res1[5];
+	u32 lauscr;	/* AUS Mode Control */
+	u32 lausccr;	/* AUS mode Cursor Control */
+	u32 res2[31 + 64*7];
+	u32 bglut;	/* Background Lookup Table */
+	u32 gwlut;	/* Graphic Window Lookup Table */
+};
+
+/* Wireless External Interface Module Registers */
+struct weim_regs {
+	u32 cscr0u;	/* Chip Select 0 Upper Register */
+	u32 cscr0l;	/* Chip Select 0 Lower Register */
+	u32 cscr0a;	/* Chip Select 0 Addition Register */
+	u32 pad0;
+	u32 cscr1u;	/* Chip Select 1 Upper Register */
+	u32 cscr1l;	/* Chip Select 1 Lower Register */
+	u32 cscr1a;	/* Chip Select 1 Addition Register */
+	u32 pad1;
+	u32 cscr2u;	/* Chip Select 2 Upper Register */
+	u32 cscr2l;	/* Chip Select 2 Lower Register */
+	u32 cscr2a;	/* Chip Select 2 Addition Register */
+	u32 pad2;
+	u32 cscr3u;	/* Chip Select 3 Upper Register */
+	u32 cscr3l;	/* Chip Select 3 Lower Register */
+	u32 cscr3a;	/* Chip Select 3 Addition Register */
+	u32 pad3;
+	u32 cscr4u;	/* Chip Select 4 Upper Register */
+	u32 cscr4l;	/* Chip Select 4 Lower Register */
+	u32 cscr4a;	/* Chip Select 4 Addition Register */
+	u32 pad4;
+	u32 cscr5u;	/* Chip Select 5 Upper Register */
+	u32 cscr5l;	/* Chip Select 5 Lower Register */
+	u32 cscr5a;	/* Chip Select 5 Addition Register */
+	u32 pad5;
+	u32 wcr;	/* WEIM Configuration Register */
+};
+
+/* Multi-Master Memory Interface */
+struct m3if_regs {
+	u32 ctl;	/* Control Register */
+	u32 wcfg0;	/* Watermark Configuration Register 0 */
+	u32 wcfg1;	/* Watermark Configuration Register1 */
+	u32 wcfg2;	/* Watermark Configuration Register2 */
+	u32 wcfg3;	/* Watermark Configuration Register 3 */
+	u32 wcfg4;	/* Watermark Configuration Register 4 */
+	u32 wcfg5;	/* Watermark Configuration Register 5 */
+	u32 wcfg6;	/* Watermark Configuration Register 6 */
+	u32 wcfg7;	/* Watermark Configuration Register 7 */
+	u32 wcsr;	/* Watermark Control and Status Register */
+	u32 scfg0;	/* Snooping Configuration Register 0 */
+	u32 scfg1;	/* Snooping Configuration Register 1 */
+	u32 scfg2;	/* Snooping Configuration Register 2 */
+	u32 ssr0;	/* Snooping Status Register 0 */
+	u32 ssr1;	/* Snooping Status Register 1 */
+	u32 res0;
+	u32 mlwe0;	/* Master Lock WEIM CS0 Register */
+	u32 mlwe1;	/* Master Lock WEIM CS1 Register */
+	u32 mlwe2;	/* Master Lock WEIM CS2 Register */
+	u32 mlwe3;	/* Master Lock WEIM CS3 Register */
+	u32 mlwe4;	/* Master Lock WEIM CS4 Register */
+	u32 mlwe5;	/* Master Lock WEIM CS5 Register */
+};
+
+/* Pulse width modulation */
+struct pwm_regs {
+	u32 cr;	/* Control Register */
+	u32 sr;	/* Status Register */
+	u32 ir;	/* Interrupt Register */
+	u32 sar;	/* Sample Register */
+	u32 pr;	/* Period Register */
+	u32 cnr;	/* Counter Register */
+};
+
+/* Enhanced Periodic Interrupt Timer */
+struct epit_regs {
+	u32 cr;	/* Control register */
+	u32 sr;	/* Status register */
+	u32 lr;	/* Load register */
+	u32 cmpr;	/* Compare register */
+	u32 cnr;	/* Counter register */
+};
+
+/* CSPI registers */
+struct cspi_regs {
+	u32 rxdata;
+	u32 txdata;
+	u32 ctrl;
+	u32 intr;
+	u32 dma;
+	u32 stat;
+	u32 period;
+	u32 test;
+};
 
 #endif
 
@@ -289,6 +409,8 @@ struct aips_regs {
 #define CCM_PERCLK_MASK		0x3f
 #define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
 #define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
+#define CCM_CRDR_BT_UART_SRC_SHIFT	29
+#define CCM_CRDR_BT_UART_SRC_MASK	7
 
 /* ESDRAM Controller register bitfields */
 #define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
@@ -345,12 +467,65 @@ struct aips_regs {
 #define WSR_UNLOCK1		0x5555
 #define WSR_UNLOCK2		0xAAAA
 
+/* MAX bits */
+#define MAX_MGPCR_AULB(x)	(((x) & 0x7) << 0)
+
+/* M3IF bits */
+#define M3IF_CTL_MRRP(x)	(((x) & 0xff) << 0)
+
+/* WEIM bits */
+/* 13 fields of the upper CS control register */
+#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
+		cnc, wsc, ew, wws, edc) \
+		((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
+		(psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
+		(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
+/* 12 fields of the lower CS control register */
+#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
+		csa, ebc, dsz, csn, psr, cre, wrap, csen) \
+		((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
+		(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
+		(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
+/* 14 fields of the additional CS control register */
+#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
+		wwu, age, cnc2, fce) \
+		((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
+		(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
+		(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
+		(age) << 2 | (cnc2) << 1 | (fce) << 0)
+
 /* Names used in GPIO driver */
 #define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
 #define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
 #define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
 #define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN		(1 << 0)
+#define MXC_CSPICTRL_MODE	(1 << 1)
+#define MXC_CSPICTRL_XCH	(1 << 2)
+#define MXC_CSPICTRL_SMC	(1 << 3)
+#define MXC_CSPICTRL_POL	(1 << 4)
+#define MXC_CSPICTRL_PHA	(1 << 5)
+#define MXC_CSPICTRL_SSCTL	(1 << 6)
+#define MXC_CSPICTRL_SSPOL	(1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_DATARATE(x)	(((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC		(1 << 7)
+#define MXC_CSPICTRL_RXOVF	(1 << 6)
+#define MXC_CSPICTRL_MAXBITS	0xfff
+#define MXC_CSPIPERIOD_32KHZ	(1 << 15)
+#define MAX_SPI_BYTES	4
+
+#define MXC_SPI_BASE_ADDRESSES \
+	IMX_CSPI1_BASE, \
+	IMX_CSPI2_BASE, \
+	IMX_CSPI3_BASE
+
 #define CHIP_REV_1_0		0x10
 #define CHIP_REV_1_1		0x11
 #define CHIP_REV_1_2		0x12
diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 5f9c90a..045ccc4 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -10,6 +10,10 @@
 #include <asm/imx-common/iomux-v3.h>
 
 enum {
+	MX6_PAD_ECSPI1_MISO__ECSPI_MISO				= IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
+	MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI				= IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
+	MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK				= IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
+	MX6_PAD_ECSPI1_SS0__GPIO4_IO11				= IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
 	MX6_PAD_SD2_CLK__USDHC2_CLK				= IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_CMD__USDHC2_CMD				= IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
 	MX6_PAD_SD2_DAT0__USDHC2_DAT0				= IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 2dfe4ef..30d9de2 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -322,6 +322,9 @@
 
 #define V_SCLK	V_OSCK
 
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK	(1 << 28)
+
 /* AUXCLKx reg fields */
 #define AUXCLK_ENABLE_MASK		(1 << 8)
 #define AUXCLK_SRCSELECT_SHIFT		1
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 19fdece..e35a81a 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -50,6 +50,7 @@
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP54XX_L4_PER_BASE + 0x6c000)
 #define UART3_BASE		(OMAP54XX_L4_PER_BASE + 0x20000)
+#define UART4_BASE		(OMAP54XX_L4_PER_BASE + 0x6e000)
 
 /* General Purpose Timers */
 #define GPT1_BASE		(OMAP54XX_L4_WKUP_BASE + 0x18000)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index d9ea71f..6ef665d 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -1,615 +1,18 @@
 /*
  * arch/arm/include/asm/arch-rmobile/r8a7790.h
  *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
- */
+*/
 
 #ifndef __ASM_ARCH_R8A7790_H
 #define __ASM_ARCH_R8A7790_H
 
-/*
- * R8A7790 I/O Addresses
- */
-#define	RWDT_BASE		0xE6020000
-#define	SWDT_BASE		0xE6030000
-#define	LBSC_BASE		0xFEC00200
-#define DBSC3_0_BASE		0xE6790000
-#define DBSC3_1_BASE		0xE67A0000
-#define TMU_BASE		0xE61E0000
-#define	GPIO5_BASE		0xE6055000
-#define SH_QSPI_BASE	0xE6B10000
-
-#define S3C_BASE		0xE6784000
-#define S3C_INT_BASE		0xE6784A00
-#define S3C_MEDIA_BASE		0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE	0xE6784BDC
-#define S3C_QOS_CCI0_BASE	0xE6784C00
-#define S3C_QOS_CCI1_BASE	0xE6784C24
-#define S3C_QOS_MXI_BASE	0xE6784C48
-#define S3C_QOS_AXI_BASE	0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE	0xE6791000
-#define DBSC3_0_QOS_R1_BASE	0xE6791100
-#define DBSC3_0_QOS_R2_BASE	0xE6791200
-#define DBSC3_0_QOS_R3_BASE	0xE6791300
-#define DBSC3_0_QOS_R4_BASE	0xE6791400
-#define DBSC3_0_QOS_R5_BASE	0xE6791500
-#define DBSC3_0_QOS_R6_BASE	0xE6791600
-#define DBSC3_0_QOS_R7_BASE	0xE6791700
-#define DBSC3_0_QOS_R8_BASE	0xE6791800
-#define DBSC3_0_QOS_R9_BASE	0xE6791900
-#define DBSC3_0_QOS_R10_BASE	0xE6791A00
-#define DBSC3_0_QOS_R11_BASE	0xE6791B00
-#define DBSC3_0_QOS_R12_BASE	0xE6791C00
-#define DBSC3_0_QOS_R13_BASE	0xE6791D00
-#define DBSC3_0_QOS_R14_BASE	0xE6791E00
-#define DBSC3_0_QOS_R15_BASE	0xE6791F00
-#define DBSC3_0_QOS_W0_BASE	0xE6792000
-#define DBSC3_0_QOS_W1_BASE	0xE6792100
-#define DBSC3_0_QOS_W2_BASE	0xE6792200
-#define DBSC3_0_QOS_W3_BASE	0xE6792300
-#define DBSC3_0_QOS_W4_BASE	0xE6792400
-#define DBSC3_0_QOS_W5_BASE	0xE6792500
-#define DBSC3_0_QOS_W6_BASE	0xE6792600
-#define DBSC3_0_QOS_W7_BASE	0xE6792700
-#define DBSC3_0_QOS_W8_BASE	0xE6792800
-#define DBSC3_0_QOS_W9_BASE	0xE6792900
-#define DBSC3_0_QOS_W10_BASE	0xE6792A00
-#define DBSC3_0_QOS_W11_BASE	0xE6792B00
-#define DBSC3_0_QOS_W12_BASE	0xE6792C00
-#define DBSC3_0_QOS_W13_BASE	0xE6792D00
-#define DBSC3_0_QOS_W14_BASE	0xE6792E00
-#define DBSC3_0_QOS_W15_BASE	0xE6792F00
-
-#define DBSC3_0_DBADJ2		0xE67900C8
-
-#define CCI_400_MAXOT_1		0xF0091110
-#define CCI_400_MAXOT_2		0xF0092110
-#define CCI_400_QOSCNTL_1	0xF009110C
-#define CCI_400_QOSCNTL_2	0xF009210C
-
-#define	MXI_BASE		0xFE960000
-#define	MXI_QOS_BASE		0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE	0xFF800300
-#define SYS_AXI_AVB_BASE	0xFF800340
-#define SYS_AXI_G2D_BASE	0xFF800540
-#define SYS_AXI_IMP0_BASE	0xFF800580
-#define SYS_AXI_IMP1_BASE	0xFF8005C0
-#define SYS_AXI_IMUX0_BASE	0xFF800600
-#define SYS_AXI_IMUX1_BASE	0xFF800640
-#define SYS_AXI_IMUX2_BASE	0xFF800680
-#define SYS_AXI_LBS_BASE	0xFF8006C0
-#define SYS_AXI_MMUDS_BASE	0xFF800700
-#define SYS_AXI_MMUM_BASE	0xFF800740
-#define SYS_AXI_MMUR_BASE	0xFF800780
-#define SYS_AXI_MMUS0_BASE	0xFF8007C0
-#define SYS_AXI_MMUS1_BASE	0xFF800800
-#define SYS_AXI_MTSB0_BASE	0xFF800880
-#define SYS_AXI_MTSB1_BASE	0xFF8008C0
-#define SYS_AXI_PCI_BASE	0xFF800900
-#define SYS_AXI_RTX_BASE	0xFF800940
-#define SYS_AXI_SDS0_BASE	0xFF800A80
-#define SYS_AXI_SDS1_BASE	0xFF800AC0
-#define SYS_AXI_USB20_BASE	0xFF800C00
-#define SYS_AXI_USB21_BASE	0xFF800C40
-#define SYS_AXI_USB22_BASE	0xFF800C80
-#define SYS_AXI_USB30_BASE	0xFF800CC0
-
-#define RT_AXI_SHX_BASE		0xFF810100
-#define RT_AXI_RDS_BASE		0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE	0xFF810200
-#define RT_AXI_STPRO_BASE	0xFF810240
-
-#define MP_AXI_ADSP_BASE	0xFF820100
-#define MP_AXI_ASDS0_BASE	0xFF8201C0
-#define MP_AXI_ASDS1_BASE	0xFF820200
-#define MP_AXI_MLP_BASE		0xFF820240
-#define MP_AXI_MMUMP_BASE	0xFF820280
-#define MP_AXI_SPU_BASE		0xFF8202C0
-#define MP_AXI_SPUC_BASE	0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
-#define SYS_AXI256_SYX_BASE	0xFF860140
-#define SYS_AXI256_MPX_BASE	0xFF860180
-#define SYS_AXI256_MXI_BASE	0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE	0xFF880100
-#define CCI_AXI_SYX2_BASE	0xFF880140
-#define CCI_AXI_MMUR_BASE	0xFF880180
-#define CCI_AXI_MMUDS_BASE	0xFF8801C0
-#define CCI_AXI_MMUM_BASE	0xFF880200
-#define CCI_AXI_MXI_BASE	0xFF880240
-#define CCI_AXI_MMUS1_BASE	0xFF880280
-#define CCI_AXI_MMUMP_BASE	0xFF8802C0
-
-#define MEDIA_AXI_JPR_BASE	0xFE964100
-#define MEDIA_AXI_JPW_BASE	0xFE966100
-#define MEDIA_AXI_GCU0R_BASE	0xFE964140
-#define MEDIA_AXI_GCU0W_BASE	0xFE966140
-#define MEDIA_AXI_GCU1R_BASE	0xFE964180
-#define MEDIA_AXI_GCU1W_BASE	0xFE966180
-#define MEDIA_AXI_TDMR_BASE	0xFE964500
-#define MEDIA_AXI_TDMW_BASE	0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
-#define MEDIA_AXI_VIN0W_BASE	0xFE966900
-#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
-#define MEDIA_AXI_IMSR_BASE	0xFE964D80
-#define MEDIA_AXI_IMSW_BASE	0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE	0xFE965100
-#define MEDIA_AXI_VSP1W_BASE	0xFE967100
-#define MEDIA_AXI_FDP1R_BASE	0xFE965140
-#define MEDIA_AXI_FDP1W_BASE	0xFE967140
-#define MEDIA_AXI_IMRR_BASE	0xFE965180
-#define MEDIA_AXI_IMRW_BASE	0xFE967180
-#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
-#define MEDIA_AXI_DU0R_BASE	0xFE965580
-#define MEDIA_AXI_DU0W_BASE	0xFE967580
-#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
-#define MEDIA_AXI_VPC0R_BASE	0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
-
-#define SYS_AXI_AVBDMSCR	0xFF802000
-#define SYS_AXI_SYX2DMSCR	0xFF802004
-#define SYS_AXI_CC50DMSCR	0xFF802008
-#define SYS_AXI_CC51DMSCR	0xFF80200C
-#define SYS_AXI_CCIDMSCR	0xFF802010
-#define SYS_AXI_CSDMSCR		0xFF802014
-#define SYS_AXI_DDMDMSCR	0xFF802018
-#define SYS_AXI_ETHDMSCR	0xFF80201C
-#define SYS_AXI_G2DDMSCR	0xFF802020
-#define SYS_AXI_IMP0DMSCR	0xFF802024
-#define SYS_AXI_IMP1DMSCR	0xFF802028
-#define SYS_AXI_LBSDMSCR	0xFF80202C
-#define SYS_AXI_MMUDSDMSCR	0xFF802030
-#define SYS_AXI_MMUMXDMSCR	0xFF802034
-#define SYS_AXI_MMURDDMSCR	0xFF802038
-#define SYS_AXI_MMUS0DMSCR	0xFF80203C
-#define SYS_AXI_MMUS1DMSCR	0xFF802040
-#define SYS_AXI_MPXDMSCR	0xFF802044
-#define SYS_AXI_MTSB0DMSCR	0xFF802048
-#define SYS_AXI_MTSB1DMSCR	0xFF80204C
-#define SYS_AXI_PCIDMSCR	0xFF802050
-#define SYS_AXI_RTXDMSCR	0xFF802054
-#define SYS_AXI_SAT0DMSCR	0xFF802058
-#define SYS_AXI_SAT1DMSCR	0xFF80205C
-#define SYS_AXI_SDM0DMSCR	0xFF802060
-#define SYS_AXI_SDM1DMSCR	0xFF802064
-#define SYS_AXI_SDS0DMSCR	0xFF802068
-#define SYS_AXI_SDS1DMSCR	0xFF80206C
-#define SYS_AXI_ETRABDMSCR	0xFF802070
-#define SYS_AXI_ETRKFDMSCR	0xFF802074
-#define SYS_AXI_UDM0DMSCR	0xFF802078
-#define SYS_AXI_UDM1DMSCR	0xFF80207C
-#define SYS_AXI_USB20DMSCR	0xFF802080
-#define SYS_AXI_USB21DMSCR	0xFF802084
-#define SYS_AXI_USB22DMSCR	0xFF802088
-#define SYS_AXI_USB30DMSCR	0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
-#define SYS_AXI_AVBSLVDMSCR	0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR	0xFF802110
-#define SYS_AXI_GICSLVDMSCR	0xFF802114
-#define SYS_AXI_IMPSLVDMSCR	0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
-#define SYS_AXI_LBSSLVDMSCR	0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
-#define SYS_AXI_MPXSLVDMSCR	0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR	0xFF802140
-#define SYS_AXI_PCISLVDMSCR	0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR	0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR	0xFF802180
-#define SYS_AXI_STBSLVDMSCR	0xFF802188
-#define SYS_AXI_STMSLVDMSCR	0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
-
-#define RT_AXI_CBMDMSCR		0xFF812000
-#define RT_AXI_DBDMSCR		0xFF812004
-#define RT_AXI_RDMDMSCR		0xFF812008
-#define RT_AXI_RDSDMSCR		0xFF81200C
-#define RT_AXI_STRDMSCR		0xFF812010
-#define RT_AXI_SY2RTDMSCR	0xFF812014
-#define RT_AXI_CBSSLVDMSCR	0xFF812100
-#define RT_AXI_DBSSLVDMSCR	0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
-
-#define MP_AXI_ADSPDMSCR	0xFF822000
-#define MP_AXI_ASDM0DMSCR	0xFF822004
-#define MP_AXI_ASDM1DMSCR	0xFF822008
-#define MP_AXI_ASDS0DMSCR	0xFF82200C
-#define MP_AXI_ASDS1DMSCR	0xFF822010
-#define MP_AXI_MLPDMSCR		0xFF822014
-#define MP_AXI_MMUMPDMSCR	0xFF822018
-#define MP_AXI_SPUDMSCR		0xFF82201C
-#define MP_AXI_SPUCDMSCR	0xFF822020
-#define MP_AXI_SY2MPDMSCR	0xFF822024
-#define MP_AXI_ADSPSLVDMSCR	0xFF822100
-#define MP_AXI_MLMSLVDMSCR	0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
-#define MP_AXI_SPUSLVDMSCR	0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR	0xFF842000
-#define ADM_AXI_ASDM1DMSCR	0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
-
-#define DM_AXI_RDMDMSCR		0xFF852000
-#define DM_AXI_SDM0DMSCR	0xFF852004
-#define DM_AXI_SDM1DMSCR	0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
-#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR	0xFF852110
-#define DM_AXI_SAP4SLVDMSCR	0xFF852114
-#define DM_AXI_SAP5SLVDMSCR	0xFF852118
-#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR	0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
-
-#define SYS_AXI256_SYXDMSCR	0xFF862000
-#define SYS_AXI256_MPXDMSCR	0xFF862004
-#define SYS_AXI256_MXIDMSCR	0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
-
-#define MXT_SYXDMSCR		0xFF872000
-#define MXT_CMM0SLVDMSCR	0xFF872100
-#define MXT_CMM1SLVDMSCR	0xFF872104
-#define MXT_CMM2SLVDMSCR	0xFF872108
-#define MXT_FDPSLVDMSCR		0xFF87210C
-#define MXT_IMRSLVDMSCR		0xFF872110
-#define MXT_VINSLVDMSCR		0xFF872114
-#define MXT_VPC0SLVDMSCR	0xFF872118
-#define MXT_VPC1SLVDMSCR	0xFF87211C
-#define MXT_VSP0SLVDMSCR	0xFF872120
-#define MXT_VSP1SLVDMSCR	0xFF872124
-#define MXT_VSPD0SLVDMSCR	0xFF872128
-#define MXT_VSPD1SLVDMSCR	0xFF87212C
-#define MXT_MAP1SLVDMSCR	0xFF872130
-#define MXT_MAP2SLVDMSCR	0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR	0xFF882000
-#define CCI_AXI_SYX2DMSCR	0xFF882004
-#define CCI_AXI_MMURDMSCR	0xFF882008
-#define CCI_AXI_MMUDSDMSCR	0xFF88200C
-#define CCI_AXI_MMUMDMSCR	0xFF882010
-#define CCI_AXI_MXIDMSCR	0xFF882014
-#define CCI_AXI_MMUS1DMSCR	0xFF882018
-#define CCI_AXI_MMUMPDMSCR	0xFF88201C
-#define CCI_AXI_DVMDMSCR	0xFF882020
-#define CCI_AXI_CCISLVDMSCR	0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR	0xFF880400
-#define CCI_AXI_IPMMURDVMCR	0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
-#define CCI_AXI_AX2ADDRMASK	0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7790_rwdt {
-	u32 rwtcnt;	/* 0x00 */
-	u32 rwtcsra;	/* 0x04 */
-	u16 rwtcsrb;	/* 0x08 */
-};
-
-/* SWDT */
-struct r8a7790_swdt {
-	u32 swtcnt;	/* 0x00 */
-	u32 swtcsra;	/* 0x04 */
-	u16 swtcsrb;	/* 0x08 */
-};
-
-/* LBSC */
-struct r8a7790_lbsc {
-	u32 cs0ctrl;
-	u32 cs1ctrl;
-	u32 ecs0ctrl;
-	u32 ecs1ctrl;
-	u32 ecs2ctrl;
-	u32 ecs3ctrl;
-	u32 ecs4ctrl;
-	u32 ecs5ctrl;
-	u32 dummy0[4];	/* 0x20 .. 0x2C */
-	u32 cswcr0;
-	u32 cswcr1;
-	u32 ecswcr0;
-	u32 ecswcr1;
-	u32 ecswcr2;
-	u32 ecswcr3;
-	u32 ecswcr4;
-	u32 ecswcr5;
-	u32 exdmawcr0;
-	u32 exdmawcr1;
-	u32 exdmawcr2;
-	u32 dummy1[9];	/* 0x5C .. 0x7C */
-	u32 cspwcr0;
-	u32 cspwcr1;
-	u32 ecspwcr0;
-	u32 ecspwcr1;
-	u32 ecspwcr2;
-	u32 ecspwcr3;
-	u32 ecspwcr4;
-	u32 ecspwcr5;
-	u32 exwtsync;
-	u32 dummy2[3];	/* 0xA4 .. 0xAC */
-	u32 cs0bstctl;
-	u32 cs0btph;
-	u32 dummy3[2];	/* 0xB8 .. 0xBC */
-	u32 cs1gdst;
-	u32 ecs0gdst;
-	u32 ecs1gdst;
-	u32 ecs2gdst;
-	u32 ecs3gdst;
-	u32 ecs4gdst;
-	u32 ecs5gdst;
-	u32 dummy4[5];	/* 0xDC .. 0xEC */
-	u32 exdmaset0;
-	u32 exdmaset1;
-	u32 exdmaset2;
-	u32 dummy5[5];	/* 0xFC .. 0x10C */
-	u32 exdmcr0;
-	u32 exdmcr1;
-	u32 exdmcr2;
-	u32 dummy6[5];	/* 0x11C .. 0x12C */
-	u32 bcintsr;
-	u32 bcintcr;
-	u32 bcintmr;
-	u32 dummy7;	/* 0x13C */
-	u32 exbatlv;
-	u32 exwtsts;
-	u32 dummy8[14];	/* 0x148 .. 0x17C */
-	u32 atacsctrl;
-	u32 dummy9[15]; /* 0x184 .. 0x1BC */
-	u32 exbct;
-	u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7790_dbsc3 {
-	u32 dummy0[3];	/* 0x00 .. 0x08 */
-	u32 dbstate1;
-	u32 dbacen;
-	u32 dbrfen;
-	u32 dbcmd;
-	u32 dbwait;
-	u32 dbkind;
-	u32 dbconf0;
-	u32 dummy1[2];	/* 0x28 .. 0x2C */
-	u32 dbphytype;
-	u32 dummy2[3];	/* 0x34 .. 0x3C */
-	u32 dbtr0;
-	u32 dbtr1;
-	u32 dbtr2;
-	u32 dummy3;	/* 0x4C */
-	u32 dbtr3;
-	u32 dbtr4;
-	u32 dbtr5;
-	u32 dbtr6;
-	u32 dbtr7;
-	u32 dbtr8;
-	u32 dbtr9;
-	u32 dbtr10;
-	u32 dbtr11;
-	u32 dbtr12;
-	u32 dbtr13;
-	u32 dbtr14;
-	u32 dbtr15;
-	u32 dbtr16;
-	u32 dbtr17;
-	u32 dbtr18;
-	u32 dbtr19;
-	u32 dummy4[7];	/* 0x94 .. 0xAC */
-	u32 dbbl;
-	u32 dummy5[3];	/* 0xB4 .. 0xBC */
-	u32 dbadj0;
-	u32 dummy6;	/* 0xC4 */
-	u32 dbadj2;
-	u32 dummy7[5];	/* 0xCC .. 0xDC */
-	u32 dbrfcnf0;
-	u32 dbrfcnf1;
-	u32 dbrfcnf2;
-	u32 dummy8[2];	/* 0xEC .. 0xF0 */
-	u32 dbcalcnf;
-	u32 dbcaltr;
-	u32 dummy9;	/* 0xFC */
-	u32 dbrnk0;
-	u32 dummy10[31];	/* 0x104 .. 0x17C */
-	u32 dbpdncnf;
-	u32 dummy11[47];	/* 0x184 ..0x23C */
-	u32 dbdfistat;
-	u32 dbdficnt;
-	u32 dummy12[14];	/* 0x248 .. 0x27C */
-	u32 dbpdlck;
-	u32 dummy13[3];	/* 0x284 .. 0x28C */
-	u32 dbpdrga;
-	u32 dummy14[3];	/* 0x294 .. 0x29C */
-	u32 dbpdrgd;
-	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
-	u32 dbbs0cnt1;
-	u32 dummy16[30];	/* 0x308 .. 0x37C */
-	u32 dbwt0cnf0;
-	u32 dbwt0cnf1;
-	u32 dbwt0cnf2;
-	u32 dbwt0cnf3;
-	u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7790_gpio {
-	u32 iointsel;
-	u32 inoutsel;
-	u32 outdt;
-	u32 indt;
-	u32 intdt;
-	u32 intclr;
-	u32 intmsk;
-	u32 posneg;
-	u32 edglevel;
-	u32 filonoff;
-	u32 intmsks;
-	u32 mskclrs;
-	u32 outdtsel;
-	u32 outdth;
-	u32 outdtl;
-	u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7790_s3c {
-	u32 s3cexcladdmsk;
-	u32 s3cexclidmsk;
-	u32 s3cadsplcr;
-	u32 s3cmaar;
-	u32 s3carcr11;
-	u32 s3crorr;
-	u32 s3cworr;
-	u32 s3carcr22;
-	u32 dummy1[2];	/* 0x20 .. 0x24 */
-	u32 s3cmctr;
-	u32 dummy2;	/* 0x2C */
-	u32 cconf0;
-	u32 cconf1;
-	u32 cconf2;
-	u32 cconf3;
-};
-
-struct r8a7790_s3c_qos {
-	u32 s3cqos0;
-	u32 s3cqos1;
-	u32 s3cqos2;
-	u32 s3cqos3;
-	u32 s3cqos4;
-	u32 s3cqos5;
-	u32 s3cqos6;
-	u32 s3cqos7;
-	u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7790_dbsc3_qos {
-	u32 dblgcnt;
-	u32 dbtmval0;
-	u32 dbtmval1;
-	u32 dbtmval2;
-	u32 dbtmval3;
-	u32 dbrqctr;
-	u32 dbthres0;
-	u32 dbthres1;
-	u32 dbthres2;
-	u32 dummy0;	/* 0x24 */
-	u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7790_mxi {
-	u32 mxsaar0;
-	u32 mxsaar1;
-	u32 dummy0[7];	/* 0x08 .. 0x20 */
-	u32 mxaxiracr;
-	u32 mxs3cracr;
-	u32 dummy1[2];	/* 0x2C .. 0x30 */
-	u32 mxaxiwacr;
-	u32 mxs3cwacr;
-	u32 dummy2;	/* 0x3C */
-	u32 mxrtcr;
-	u32 mxwtcr;
-};
-
-struct r8a7790_mxi_qos {
-	u32 vspdu0;
-	u32 vspdu1;
-	u32 du0;
-	u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7790_axi_qos {
-	u32 qosconf;
-	u32 qosctset0;
-	u32 qosctset1;
-	u32 qosctset2;
-	u32 qosctset3;
-	u32 qosreqctr;
-	u32 qosthres0;
-	u32 qosthres1;
-	u32 qosthres2;
-	u32 qosqon;
-};
+#include "rcar-base.h"
 
-#endif
+#define R8A7790_CUT_ES2X	2
+#define IS_R8A7790_ES2()	\
+	(rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
 
 #endif /* __ASM_ARCH_R8A7790_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index ff30180..4791825 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -1,69 +1,18 @@
 /*
  * arch/arm/include/asm/arch-rmobile/r8a7791.h
  *
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0
- */
+*/
 
 #ifndef __ASM_ARCH_R8A7791_H
 #define __ASM_ARCH_R8A7791_H
 
+#include "rcar-base.h"
 /*
- * R8A7791 I/O Addresses
+ * R-Car (R8A7791) I/O Addresses
  */
-#define	RWDT_BASE	0xE6020000
-#define	SWDT_BASE	0xE6030000
-#define	LBSC_BASE	0xFEC00200
-#define DBSC3_0_BASE	0xE6790000
-#define DBSC3_1_BASE	0xE67A0000
-#define TMU_BASE	0xE61E0000
-#define	GPIO5_BASE	0xE6055000
-#define SH_QSPI_BASE	0xE6B10000
-
-#define S3C_BASE	0xE6784000
-#define S3C_INT_BASE	0xE6784A00
-#define S3C_MEDIA_BASE	0xE6784B00
-
-#define S3C_QOS_DCACHE_BASE	0xE6784BDC
-#define S3C_QOS_CCI0_BASE	0xE6784C00
-#define S3C_QOS_CCI1_BASE	0xE6784C24
-#define S3C_QOS_MXI_BASE	0xE6784C48
-#define S3C_QOS_AXI_BASE	0xE6784C6C
-
-#define DBSC3_0_QOS_R0_BASE	0xE6791000
-#define DBSC3_0_QOS_R1_BASE	0xE6791100
-#define DBSC3_0_QOS_R2_BASE	0xE6791200
-#define DBSC3_0_QOS_R3_BASE	0xE6791300
-#define DBSC3_0_QOS_R4_BASE	0xE6791400
-#define DBSC3_0_QOS_R5_BASE	0xE6791500
-#define DBSC3_0_QOS_R6_BASE	0xE6791600
-#define DBSC3_0_QOS_R7_BASE	0xE6791700
-#define DBSC3_0_QOS_R8_BASE	0xE6791800
-#define DBSC3_0_QOS_R9_BASE	0xE6791900
-#define DBSC3_0_QOS_R10_BASE	0xE6791A00
-#define DBSC3_0_QOS_R11_BASE	0xE6791B00
-#define DBSC3_0_QOS_R12_BASE	0xE6791C00
-#define DBSC3_0_QOS_R13_BASE	0xE6791D00
-#define DBSC3_0_QOS_R14_BASE	0xE6791E00
-#define DBSC3_0_QOS_R15_BASE	0xE6791F00
-#define DBSC3_0_QOS_W0_BASE	0xE6792000
-#define DBSC3_0_QOS_W1_BASE	0xE6792100
-#define DBSC3_0_QOS_W2_BASE	0xE6792200
-#define DBSC3_0_QOS_W3_BASE	0xE6792300
-#define DBSC3_0_QOS_W4_BASE	0xE6792400
-#define DBSC3_0_QOS_W5_BASE	0xE6792500
-#define DBSC3_0_QOS_W6_BASE	0xE6792600
-#define DBSC3_0_QOS_W7_BASE	0xE6792700
-#define DBSC3_0_QOS_W8_BASE	0xE6792800
-#define DBSC3_0_QOS_W9_BASE	0xE6792900
-#define DBSC3_0_QOS_W10_BASE	0xE6792A00
-#define DBSC3_0_QOS_W11_BASE	0xE6792B00
-#define DBSC3_0_QOS_W12_BASE	0xE6792C00
-#define DBSC3_0_QOS_W13_BASE	0xE6792D00
-#define DBSC3_0_QOS_W14_BASE	0xE6792E00
-#define DBSC3_0_QOS_W15_BASE	0xE6792F00
-
 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
 #define DBSC3_1_QOS_R1_BASE	0xE67A1100
 #define DBSC3_1_QOS_R2_BASE	0xE67A1200
@@ -97,569 +46,8 @@
 #define DBSC3_1_QOS_W14_BASE	0xE67A2E00
 #define DBSC3_1_QOS_W15_BASE	0xE67A2F00
 
-#define DBSC3_0_DBADJ2		0xE67900C8
-
-#define CCI_400_MAXOT_1		0xF0091110
-#define CCI_400_MAXOT_2		0xF0092110
-#define CCI_400_QOSCNTL_1	0xF009110C
-#define CCI_400_QOSCNTL_2	0xF009210C
-
-#define	MXI_BASE		0xFE960000
-#define	MXI_QOS_BASE		0xFE960300
-
-#define SYS_AXI_SYX64TO128_BASE	0xFF800300
-#define SYS_AXI_AVB_BASE	0xFF800340
-#define SYS_AXI_G2D_BASE	0xFF800540
-#define SYS_AXI_IMP0_BASE	0xFF800580
-#define SYS_AXI_IMP1_BASE	0xFF8005C0
-#define SYS_AXI_IMUX0_BASE	0xFF800600
-#define SYS_AXI_IMUX1_BASE	0xFF800640
-#define SYS_AXI_IMUX2_BASE	0xFF800680
-#define SYS_AXI_LBS_BASE	0xFF8006C0
-#define SYS_AXI_MMUDS_BASE	0xFF800700
-#define SYS_AXI_MMUM_BASE	0xFF800740
-#define SYS_AXI_MMUR_BASE	0xFF800780
-#define SYS_AXI_MMUS0_BASE	0xFF8007C0
-#define SYS_AXI_MMUS1_BASE	0xFF800800
-#define SYS_AXI_MTSB0_BASE	0xFF800880
-#define SYS_AXI_MTSB1_BASE	0xFF8008C0
-#define SYS_AXI_PCI_BASE	0xFF800900
-#define SYS_AXI_RTX_BASE	0xFF800940
-#define SYS_AXI_SDS0_BASE	0xFF800A80
-#define SYS_AXI_SDS1_BASE	0xFF800AC0
-#define SYS_AXI_USB20_BASE	0xFF800C00
-#define SYS_AXI_USB21_BASE	0xFF800C40
-#define SYS_AXI_USB22_BASE	0xFF800C80
-#define SYS_AXI_USB30_BASE	0xFF800CC0
-#define SYS_AXI_AX2M_BASE	0xFF800380
-#define SYS_AXI_CC50_BASE	0xFF8003C0
-#define SYS_AXI_CCI_BASE	0xFF800440
-#define SYS_AXI_CS_BASE		0xFF800480
-#define SYS_AXI_DDM_BASE	0xFF8004C0
-#define SYS_AXI_ETH_BASE	0xFF800500
-#define SYS_AXI_MPXM_BASE	0xFF800840
-#define SYS_AXI_SAT0_BASE	0xFF800980
-#define SYS_AXI_SAT1_BASE	0xFF8009C0
-#define SYS_AXI_SDM0_BASE	0xFF800A00
-#define SYS_AXI_SDM1_BASE	0xFF800A40
-#define SYS_AXI_TRAB_BASE	0xFF800B00
-#define SYS_AXI_UDM0_BASE	0xFF800B80
-#define SYS_AXI_UDM1_BASE	0xFF800BC0
-
-#define RT_AXI_SHX_BASE		0xFF810100
-#define RT_AXI_DBG_BASE		0xFF810140
-#define RT_AXI_RDM_BASE		0xFF810180
-#define RT_AXI_RDS_BASE		0xFF8101C0
-#define RT_AXI_RTX64TO128_BASE	0xFF810200
-#define RT_AXI_STPRO_BASE	0xFF810240
-#define RT_AXI_SY2RT_BASE	0xFF810280
-
-#define MP_AXI_ADSP_BASE	0xFF820100
-#define MP_AXI_ASDS0_BASE	0xFF8201C0
-#define MP_AXI_ASDS1_BASE	0xFF820200
-#define MP_AXI_MLP_BASE		0xFF820240
-#define MP_AXI_MMUMP_BASE	0xFF820280
-#define MP_AXI_SPU_BASE		0xFF8202C0
-#define MP_AXI_SPUC_BASE	0xFF820300
-
-#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
-#define SYS_AXI256_SYX_BASE	0xFF860140
-#define SYS_AXI256_MPX_BASE	0xFF860180
-#define SYS_AXI256_MXI_BASE	0xFF8601C0
-
-#define CCI_AXI_MMUS0_BASE	0xFF880100
-#define CCI_AXI_SYX2_BASE	0xFF880140
-#define CCI_AXI_MMUR_BASE	0xFF880180
-#define CCI_AXI_MMUDS_BASE	0xFF8801C0
-#define CCI_AXI_MMUM_BASE	0xFF880200
-#define CCI_AXI_MXI_BASE	0xFF880240
-#define CCI_AXI_MMUS1_BASE	0xFF880280
-#define CCI_AXI_MMUMP_BASE	0xFF8802C0
-
-#define MEDIA_AXI_MXR_BASE	0xFE960080
-#define MEDIA_AXI_MXW_BASE	0xFE9600C0
-#define MEDIA_AXI_JPR_BASE	0xFE964100
-#define MEDIA_AXI_JPW_BASE	0xFE966100
-#define MEDIA_AXI_GCU0R_BASE	0xFE964140
-#define MEDIA_AXI_GCU0W_BASE	0xFE966140
-#define MEDIA_AXI_GCU1R_BASE	0xFE964180
-#define MEDIA_AXI_GCU1W_BASE	0xFE966180
-#define MEDIA_AXI_TDMR_BASE	0xFE964500
-#define MEDIA_AXI_TDMW_BASE	0xFE966500
-#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
-#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
-#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
-#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
-#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
-#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
-#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
-#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
-#define MEDIA_AXI_VIN0W_BASE	0xFE966900
-#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
-#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
-#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
-#define MEDIA_AXI_IMSR_BASE	0xFE964D80
-#define MEDIA_AXI_IMSW_BASE	0xFE966D80
-#define MEDIA_AXI_VSP1R_BASE	0xFE965100
-#define MEDIA_AXI_VSP1W_BASE	0xFE967100
-#define MEDIA_AXI_FDP1R_BASE	0xFE965140
-#define MEDIA_AXI_FDP1W_BASE	0xFE967140
-#define MEDIA_AXI_IMRR_BASE	0xFE965180
-#define MEDIA_AXI_IMRW_BASE	0xFE967180
-#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
-#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
-#define MEDIA_AXI_DU0R_BASE	0xFE965580
-#define MEDIA_AXI_DU0W_BASE	0xFE967580
-#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
-#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
-#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
-#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
-#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
-#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
-#define MEDIA_AXI_VPC0R_BASE	0xFE965980
-#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
-#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
-#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
-#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
-#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
-
-#define SYS_AXI_AVBDMSCR	0xFF802000
-#define SYS_AXI_SYX2DMSCR	0xFF802004
-#define SYS_AXI_CC50DMSCR	0xFF802008
-#define SYS_AXI_CC51DMSCR	0xFF80200C
-#define SYS_AXI_CCIDMSCR	0xFF802010
-#define SYS_AXI_CSDMSCR		0xFF802014
-#define SYS_AXI_DDMDMSCR	0xFF802018
-#define SYS_AXI_ETHDMSCR	0xFF80201C
-#define SYS_AXI_G2DDMSCR	0xFF802020
-#define SYS_AXI_IMP0DMSCR	0xFF802024
-#define SYS_AXI_IMP1DMSCR	0xFF802028
-#define SYS_AXI_LBSDMSCR	0xFF80202C
-#define SYS_AXI_MMUDSDMSCR	0xFF802030
-#define SYS_AXI_MMUMXDMSCR	0xFF802034
-#define SYS_AXI_MMURDDMSCR	0xFF802038
-#define SYS_AXI_MMUS0DMSCR	0xFF80203C
-#define SYS_AXI_MMUS1DMSCR	0xFF802040
-#define SYS_AXI_MPXDMSCR	0xFF802044
-#define SYS_AXI_MTSB0DMSCR	0xFF802048
-#define SYS_AXI_MTSB1DMSCR	0xFF80204C
-#define SYS_AXI_PCIDMSCR	0xFF802050
-#define SYS_AXI_RTXDMSCR	0xFF802054
-#define SYS_AXI_SAT0DMSCR	0xFF802058
-#define SYS_AXI_SAT1DMSCR	0xFF80205C
-#define SYS_AXI_SDM0DMSCR	0xFF802060
-#define SYS_AXI_SDM1DMSCR	0xFF802064
-#define SYS_AXI_SDS0DMSCR	0xFF802068
-#define SYS_AXI_SDS1DMSCR	0xFF80206C
-#define SYS_AXI_ETRABDMSCR	0xFF802070
-#define SYS_AXI_ETRKFDMSCR	0xFF802074
-#define SYS_AXI_UDM0DMSCR	0xFF802078
-#define SYS_AXI_UDM1DMSCR	0xFF80207C
-#define SYS_AXI_USB20DMSCR	0xFF802080
-#define SYS_AXI_USB21DMSCR	0xFF802084
-#define SYS_AXI_USB22DMSCR	0xFF802088
-#define SYS_AXI_USB30DMSCR	0xFF80208C
-#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
-#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
-#define SYS_AXI_AVBSLVDMSCR	0xFF802108
-#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
-#define SYS_AXI_ETHSLVDMSCR	0xFF802110
-#define SYS_AXI_GICSLVDMSCR	0xFF802114
-#define SYS_AXI_IMPSLVDMSCR	0xFF802118
-#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
-#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
-#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
-#define SYS_AXI_LBSSLVDMSCR	0xFF802128
-#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
-#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
-#define SYS_AXI_MPXSLVDMSCR	0xFF802134
-#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
-#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
-#define SYS_AXI_MXTSLVDMSCR	0xFF802140
-#define SYS_AXI_PCISLVDMSCR	0xFF802144
-#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
-#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
-#define SYS_AXI_RTXSLVDMSCR	0xFF802150
-#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
-#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
-#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
-#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
-#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
-#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
-#define SYS_AXI_SGXSLVDMSCR	0xFF802180
-#define SYS_AXI_STBSLVDMSCR	0xFF802188
-#define SYS_AXI_STMSLVDMSCR	0xFF80218C
-#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
-#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
-#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
-#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
-#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
-#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
-#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
-
-#define RT_AXI_CBMDMSCR		0xFF812000
-#define RT_AXI_DBDMSCR		0xFF812004
-#define RT_AXI_RDMDMSCR		0xFF812008
-#define RT_AXI_RDSDMSCR		0xFF81200C
-#define RT_AXI_STRDMSCR		0xFF812010
-#define RT_AXI_SY2RTDMSCR	0xFF812014
-#define RT_AXI_CBSSLVDMSCR	0xFF812100
-#define RT_AXI_DBSSLVDMSCR	0xFF812104
-#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
-#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
-#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
-#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
-#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
-#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
-#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
-#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
-
-#define MP_AXI_ADSPDMSCR	0xFF822000
-#define MP_AXI_ASDM0DMSCR	0xFF822004
-#define MP_AXI_ASDM1DMSCR	0xFF822008
-#define MP_AXI_ASDS0DMSCR	0xFF82200C
-#define MP_AXI_ASDS1DMSCR	0xFF822010
-#define MP_AXI_MLPDMSCR		0xFF822014
-#define MP_AXI_MMUMPDMSCR	0xFF822018
-#define MP_AXI_SPUDMSCR		0xFF82201C
-#define MP_AXI_SPUCDMSCR	0xFF822020
-#define MP_AXI_SY2MPDMSCR	0xFF822024
-#define MP_AXI_ADSPSLVDMSCR	0xFF822100
-#define MP_AXI_MLMSLVDMSCR	0xFF822104
-#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
-#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
-#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
-#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
-#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
-#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
-#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
-#define MP_AXI_SPUSLVDMSCR	0xFF822128
-#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
-
-#define ADM_AXI_ASDM0DMSCR	0xFF842000
-#define ADM_AXI_ASDM1DMSCR	0xFF842004
-#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
-#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
-#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
-
-#define DM_AXI_RDMDMSCR		0xFF852000
-#define DM_AXI_SDM0DMSCR	0xFF852004
-#define DM_AXI_SDM1DMSCR	0xFF852008
-#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
-#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
-#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
-#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
-#define DM_AXI_RAP5SLVDMSCR	0xFF852110
-#define DM_AXI_SAP4SLVDMSCR	0xFF852114
-#define DM_AXI_SAP5SLVDMSCR	0xFF852118
-#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
-#define DM_AXI_SAP65SLVDMSCR	0xFF852120
-#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
-#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
-#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
-#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
-
-#define SYS_AXI256_SYXDMSCR	0xFF862000
-#define SYS_AXI256_MPXDMSCR	0xFF862004
-#define SYS_AXI256_MXIDMSCR	0xFF862008
-#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
-#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
-#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
-#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
-#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
-
-#define MXT_SYXDMSCR		0xFF872000
-#define MXT_CMM0SLVDMSCR	0xFF872100
-#define MXT_CMM1SLVDMSCR	0xFF872104
-#define MXT_CMM2SLVDMSCR	0xFF872108
-#define MXT_FDPSLVDMSCR		0xFF87210C
-#define MXT_IMRSLVDMSCR		0xFF872110
-#define MXT_VINSLVDMSCR		0xFF872114
-#define MXT_VPC0SLVDMSCR	0xFF872118
-#define MXT_VPC1SLVDMSCR	0xFF87211C
-#define MXT_VSP0SLVDMSCR	0xFF872120
-#define MXT_VSP1SLVDMSCR	0xFF872124
-#define MXT_VSPD0SLVDMSCR	0xFF872128
-#define MXT_VSPD1SLVDMSCR	0xFF87212C
-#define MXT_MAP1SLVDMSCR	0xFF872130
-#define MXT_MAP2SLVDMSCR	0xFF872134
-
-#define CCI_AXI_MMUS0DMSCR	0xFF882000
-#define CCI_AXI_SYX2DMSCR	0xFF882004
-#define CCI_AXI_MMURDMSCR	0xFF882008
-#define CCI_AXI_MMUDSDMSCR	0xFF88200C
-#define CCI_AXI_MMUMDMSCR	0xFF882010
-#define CCI_AXI_MXIDMSCR	0xFF882014
-#define CCI_AXI_MMUS1DMSCR	0xFF882018
-#define CCI_AXI_MMUMPDMSCR	0xFF88201C
-#define CCI_AXI_DVMDMSCR	0xFF882020
-#define CCI_AXI_CCISLVDMSCR	0xFF882100
-
-#define CCI_AXI_IPMMUIDVMCR	0xFF880400
-#define CCI_AXI_IPMMURDVMCR	0xFF880404
-#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
-#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
-#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
-#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
-#define CCI_AXI_AX2ADDRMASK	0xFF88041C
-
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-
-/* RWDT */
-struct r8a7791_rwdt {
-	u32 rwtcnt;	/* 0x00 */
-	u32 rwtcsra;	/* 0x04 */
-	u16 rwtcsrb;	/* 0x08 */
-};
-
-/* SWDT */
-struct r8a7791_swdt {
-	u32 swtcnt;	/* 0x00 */
-	u32 swtcsra;	/* 0x04 */
-	u16 swtcsrb;	/* 0x08 */
-};
-
-/* LBSC */
-struct r8a7791_lbsc {
-	u32 cs0ctrl;
-	u32 cs1ctrl;
-	u32 ecs0ctrl;
-	u32 ecs1ctrl;
-	u32 ecs2ctrl;
-	u32 ecs3ctrl;
-	u32 ecs4ctrl;
-	u32 ecs5ctrl;
-	u32 dummy0[4];	/* 0x20 .. 0x2C */
-	u32 cswcr0;
-	u32 cswcr1;
-	u32 ecswcr0;
-	u32 ecswcr1;
-	u32 ecswcr2;
-	u32 ecswcr3;
-	u32 ecswcr4;
-	u32 ecswcr5;
-	u32 exdmawcr0;
-	u32 exdmawcr1;
-	u32 exdmawcr2;
-	u32 dummy1[9];	/* 0x5C .. 0x7C */
-	u32 cspwcr0;
-	u32 cspwcr1;
-	u32 ecspwcr0;
-	u32 ecspwcr1;
-	u32 ecspwcr2;
-	u32 ecspwcr3;
-	u32 ecspwcr4;
-	u32 ecspwcr5;
-	u32 exwtsync;
-	u32 dummy2[3];	/* 0xA4 .. 0xAC */
-	u32 cs0bstctl;
-	u32 cs0btph;
-	u32 dummy3[2];	/* 0xB8 .. 0xBC */
-	u32 cs1gdst;
-	u32 ecs0gdst;
-	u32 ecs1gdst;
-	u32 ecs2gdst;
-	u32 ecs3gdst;
-	u32 ecs4gdst;
-	u32 ecs5gdst;
-	u32 dummy4[5];	/* 0xDC .. 0xEC */
-	u32 exdmaset0;
-	u32 exdmaset1;
-	u32 exdmaset2;
-	u32 dummy5[5];	/* 0xFC .. 0x10C */
-	u32 exdmcr0;
-	u32 exdmcr1;
-	u32 exdmcr2;
-	u32 dummy6[5];	/* 0x11C .. 0x12C */
-	u32 bcintsr;
-	u32 bcintcr;
-	u32 bcintmr;
-	u32 dummy7;	/* 0x13C */
-	u32 exbatlv;
-	u32 exwtsts;
-	u32 dummy8[14];	/* 0x148 .. 0x17C */
-	u32 atacsctrl;
-	u32 dummy9[15]; /* 0x184 .. 0x1BC */
-	u32 exbct;
-	u32 extct;
-};
-
-/* DBSC3 */
-struct r8a7791_dbsc3 {
-	u32 dummy0[3];	/* 0x00 .. 0x08 */
-	u32 dbstate1;
-	u32 dbacen;
-	u32 dbrfen;
-	u32 dbcmd;
-	u32 dbwait;
-	u32 dbkind;
-	u32 dbconf0;
-	u32 dummy1[2];	/* 0x28 .. 0x2C */
-	u32 dbphytype;
-	u32 dummy2[3];	/* 0x34 .. 0x3C */
-	u32 dbtr0;
-	u32 dbtr1;
-	u32 dbtr2;
-	u32 dummy3;	/* 0x4C */
-	u32 dbtr3;
-	u32 dbtr4;
-	u32 dbtr5;
-	u32 dbtr6;
-	u32 dbtr7;
-	u32 dbtr8;
-	u32 dbtr9;
-	u32 dbtr10;
-	u32 dbtr11;
-	u32 dbtr12;
-	u32 dbtr13;
-	u32 dbtr14;
-	u32 dbtr15;
-	u32 dbtr16;
-	u32 dbtr17;
-	u32 dbtr18;
-	u32 dbtr19;
-	u32 dummy4[7];	/* 0x94 .. 0xAC */
-	u32 dbbl;
-	u32 dummy5[3];	/* 0xB4 .. 0xBC */
-	u32 dbadj0;
-	u32 dummy6;	/* 0xC4 */
-	u32 dbadj2;
-	u32 dummy7[5];	/* 0xCC .. 0xDC */
-	u32 dbrfcnf0;
-	u32 dbrfcnf1;
-	u32 dbrfcnf2;
-	u32 dummy8[2];	/* 0xEC .. 0xF0 */
-	u32 dbcalcnf;
-	u32 dbcaltr;
-	u32 dummy9;	/* 0xFC */
-	u32 dbrnk0;
-	u32 dummy10[31];	/* 0x104 .. 0x17C */
-	u32 dbpdncnf;
-	u32 dummy11[47];	/* 0x184 ..0x23C */
-	u32 dbdfistat;
-	u32 dbdficnt;
-	u32 dummy12[14];	/* 0x248 .. 0x27C */
-	u32 dbpdlck;
-	u32 dummy13[3];	/* 0x284 .. 0x28C */
-	u32 dbpdrga;
-	u32 dummy14[3];	/* 0x294 .. 0x29C */
-	u32 dbpdrgd;
-	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
-	u32 dbbs0cnt1;
-	u32 dummy16[30];	/* 0x308 .. 0x37C */
-	u32 dbwt0cnf0;
-	u32 dbwt0cnf1;
-	u32 dbwt0cnf2;
-	u32 dbwt0cnf3;
-	u32 dbwt0cnf4;
-};
-
-/* GPIO */
-struct r8a7791_gpio {
-	u32 iointsel;
-	u32 inoutsel;
-	u32 outdt;
-	u32 indt;
-	u32 intdt;
-	u32 intclr;
-	u32 intmsk;
-	u32 posneg;
-	u32 edglevel;
-	u32 filonoff;
-	u32 intmsks;
-	u32 mskclrs;
-	u32 outdtsel;
-	u32 outdth;
-	u32 outdtl;
-	u32 bothedge;
-};
-
-/* S3C(QoS) */
-struct r8a7791_s3c {
-	u32 s3cexcladdmsk;
-	u32 s3cexclidmsk;
-	u32 s3cadsplcr;
-	u32 s3cmaar;
-	u32 dummy0;	/* 0x10 */
-	u32 s3crorr;
-	u32 s3cworr;
-	u32 s3carcr22;
-	u32 dummy1[2];	/* 0x20 .. 0x24 */
-	u32 s3cmctr;
-	u32 dummy2;	/* 0x2C */
-	u32 cconf0;
-	u32 cconf1;
-	u32 cconf2;
-	u32 cconf3;
-};
-
-struct r8a7791_s3c_qos {
-	u32 s3cqos0;
-	u32 s3cqos1;
-	u32 s3cqos2;
-	u32 s3cqos3;
-	u32 s3cqos4;
-	u32 s3cqos5;
-	u32 s3cqos6;
-	u32 s3cqos7;
-	u32 s3cqos8;
-};
-
-/* DBSC(QoS) */
-struct r8a7791_dbsc3_qos {
-	u32 dblgcnt;
-	u32 dbtmval0;
-	u32 dbtmval1;
-	u32 dbtmval2;
-	u32 dbtmval3;
-	u32 dbrqctr;
-	u32 dbthres0;
-	u32 dbthres1;
-	u32 dbthres2;
-	u32 dummy0;	/* 0x24 */
-	u32 dblgqon;
-};
-
-/* MXI(QoS) */
-struct r8a7791_mxi {
-	u32 mxsaar0;
-	u32 mxsaar1;
-	u32 dummy0[8];	/* 0x08 .. 0x24 */
-	u32 mxs3cracr;
-	u32 dummy1[3];	/* 0x2C .. 0x34 */
-	u32 mxs3cwacr;
-	u32 dummy2;	/* 0x3C */
-	u32 mxrtcr;
-	u32 mxwtcr;
-};
-
-struct r8a7791_mxi_qos {
-	u32 vspdu0;
-	u32 vspdu1;
-	u32 du0;
-	u32 du1;
-};
-
-/* AXI(QoS) */
-struct r8a7791_axi_qos {
-	u32 qosconf;
-	u32 qosctset0;
-	u32 qosctset1;
-	u32 qosctset2;
-	u32 qosctset3;
-	u32 qosreqctr;
-	u32 qosthres0;
-	u32 qosthres1;
-	u32 qosthres2;
-	u32 qosqon;
-};
-
-#endif
+#define R8A7791_CUT_ES2X	2
+#define IS_R8A7791_ES2()	\
+	(rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
 
 #endif /* __ASM_ARCH_R8A7791_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
new file mode 100644
index 0000000..4331d31
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -0,0 +1,637 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/rcar-base.h
+ *
+ * Copyright (C) 2013,2014 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_RCAR_BASE_H
+#define __ASM_ARCH_RCAR_BASE_H
+
+/*
+ * R-Car (R8A7790/R8A7791) I/O Addresses
+ */
+#define RWDT_BASE		0xE6020000
+#define SWDT_BASE		0xE6030000
+#define LBSC_BASE		0xFEC00200
+#define DBSC3_0_BASE		0xE6790000
+#define DBSC3_1_BASE		0xE67A0000
+#define TMU_BASE		0xE61E0000
+#define GPIO5_BASE		0xE6055000
+#define SH_QSPI_BASE		0xE6B10000
+
+#define S3C_BASE		0xE6784000
+#define S3C_INT_BASE		0xE6784A00
+#define S3C_MEDIA_BASE		0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE	0xE6784BDC
+#define S3C_QOS_CCI0_BASE	0xE6784C00
+#define S3C_QOS_CCI1_BASE	0xE6784C24
+#define S3C_QOS_MXI_BASE	0xE6784C48
+#define S3C_QOS_AXI_BASE	0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE	0xE6791000
+#define DBSC3_0_QOS_R1_BASE	0xE6791100
+#define DBSC3_0_QOS_R2_BASE	0xE6791200
+#define DBSC3_0_QOS_R3_BASE	0xE6791300
+#define DBSC3_0_QOS_R4_BASE	0xE6791400
+#define DBSC3_0_QOS_R5_BASE	0xE6791500
+#define DBSC3_0_QOS_R6_BASE	0xE6791600
+#define DBSC3_0_QOS_R7_BASE	0xE6791700
+#define DBSC3_0_QOS_R8_BASE	0xE6791800
+#define DBSC3_0_QOS_R9_BASE	0xE6791900
+#define DBSC3_0_QOS_R10_BASE	0xE6791A00
+#define DBSC3_0_QOS_R11_BASE	0xE6791B00
+#define DBSC3_0_QOS_R12_BASE	0xE6791C00
+#define DBSC3_0_QOS_R13_BASE	0xE6791D00
+#define DBSC3_0_QOS_R14_BASE	0xE6791E00
+#define DBSC3_0_QOS_R15_BASE	0xE6791F00
+#define DBSC3_0_QOS_W0_BASE	0xE6792000
+#define DBSC3_0_QOS_W1_BASE	0xE6792100
+#define DBSC3_0_QOS_W2_BASE	0xE6792200
+#define DBSC3_0_QOS_W3_BASE	0xE6792300
+#define DBSC3_0_QOS_W4_BASE	0xE6792400
+#define DBSC3_0_QOS_W5_BASE	0xE6792500
+#define DBSC3_0_QOS_W6_BASE	0xE6792600
+#define DBSC3_0_QOS_W7_BASE	0xE6792700
+#define DBSC3_0_QOS_W8_BASE	0xE6792800
+#define DBSC3_0_QOS_W9_BASE	0xE6792900
+#define DBSC3_0_QOS_W10_BASE	0xE6792A00
+#define DBSC3_0_QOS_W11_BASE	0xE6792B00
+#define DBSC3_0_QOS_W12_BASE	0xE6792C00
+#define DBSC3_0_QOS_W13_BASE	0xE6792D00
+#define DBSC3_0_QOS_W14_BASE	0xE6792E00
+#define DBSC3_0_QOS_W15_BASE	0xE6792F00
+#define DBSC3_0_DBADJ2		0xE67900C8
+
+#define CCI_400_MAXOT_1		0xF0091110
+#define CCI_400_MAXOT_2		0xF0092110
+#define CCI_400_QOSCNTL_1	0xF009110C
+#define CCI_400_QOSCNTL_2	0xF009210C
+
+#define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE	0xFF800300
+#define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_G2D_BASE	0xFF800540
+#define SYS_AXI_IMP0_BASE	0xFF800580
+#define SYS_AXI_IMP1_BASE	0xFF8005C0
+#define SYS_AXI_IMUX0_BASE	0xFF800600
+#define SYS_AXI_IMUX1_BASE	0xFF800640
+#define SYS_AXI_IMUX2_BASE	0xFF800680
+#define SYS_AXI_LBS_BASE	0xFF8006C0
+#define SYS_AXI_MMUDS_BASE	0xFF800700
+#define SYS_AXI_MMUM_BASE	0xFF800740
+#define SYS_AXI_MMUR_BASE	0xFF800780
+#define SYS_AXI_MMUS0_BASE	0xFF8007C0
+#define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MTSB0_BASE	0xFF800880
+#define SYS_AXI_MTSB1_BASE	0xFF8008C0
+#define SYS_AXI_PCI_BASE	0xFF800900
+#define SYS_AXI_RTX_BASE	0xFF800940
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+#define SYS_AXI_AX2M_BASE	0xFF800380
+#define SYS_AXI_CC50_BASE	0xFF8003C0
+#define SYS_AXI_CCI_BASE	0xFF800440
+#define SYS_AXI_CS_BASE		0xFF800480
+#define SYS_AXI_DDM_BASE	0xFF8004C0
+#define SYS_AXI_ETH_BASE	0xFF800500
+#define SYS_AXI_MPXM_BASE	0xFF800840
+#define SYS_AXI_SAT0_BASE	0xFF800980
+#define SYS_AXI_SAT1_BASE	0xFF8009C0
+#define SYS_AXI_SDM0_BASE	0xFF800A00
+#define SYS_AXI_SDM1_BASE	0xFF800A40
+#define SYS_AXI_TRAB_BASE	0xFF800B00
+#define SYS_AXI_UDM0_BASE	0xFF800B80
+#define SYS_AXI_UDM1_BASE	0xFF800BC0
+
+#define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_DBG_BASE		0xFF810140 /* R8A7791 only */
+#define RT_AXI_RDM_BASE		0xFF810180 /* R8A7791 only */
+#define RT_AXI_RDS_BASE		0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE	0xFF810200
+#define RT_AXI_STPRO_BASE	0xFF810240
+#define RT_AXI_SY2RT_BASE	0xFF810280 /* R8A7791 only */
+
+#define MP_AXI_ADSP_BASE	0xFF820100
+#define MP_AXI_ASDS0_BASE	0xFF8201C0
+#define MP_AXI_ASDS1_BASE	0xFF820200
+#define MP_AXI_MLP_BASE		0xFF820240
+#define MP_AXI_MMUMP_BASE	0xFF820280
+#define MP_AXI_SPU_BASE		0xFF8202C0
+#define MP_AXI_SPUC_BASE	0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
+#define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_MPX_BASE	0xFF860180
+#define SYS_AXI256_MXI_BASE	0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE	0xFF880100
+#define CCI_AXI_SYX2_BASE	0xFF880140
+#define CCI_AXI_MMUR_BASE	0xFF880180
+#define CCI_AXI_MMUDS_BASE	0xFF8801C0
+#define CCI_AXI_MMUM_BASE	0xFF880200
+#define CCI_AXI_MXI_BASE	0xFF880240
+#define CCI_AXI_MMUS1_BASE	0xFF880280
+#define CCI_AXI_MMUMP_BASE	0xFF8802C0
+
+#define MEDIA_AXI_MXR_BASE	0xFE960080 /* R8A7791 only */
+#define MEDIA_AXI_MXW_BASE	0xFE9600C0 /* R8A7791 only */
+#define MEDIA_AXI_JPR_BASE	0xFE964100
+#define MEDIA_AXI_JPW_BASE	0xFE966100
+#define MEDIA_AXI_GCU0R_BASE	0xFE964140
+#define MEDIA_AXI_GCU0W_BASE	0xFE966140
+#define MEDIA_AXI_GCU1R_BASE	0xFE964180
+#define MEDIA_AXI_GCU1W_BASE	0xFE966180
+#define MEDIA_AXI_TDMR_BASE	0xFE964500
+#define MEDIA_AXI_TDMW_BASE	0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
+#define MEDIA_AXI_IMSR_BASE	0xFE964D80
+#define MEDIA_AXI_IMSW_BASE	0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE	0xFE965100
+#define MEDIA_AXI_VSP1W_BASE	0xFE967100
+#define MEDIA_AXI_FDP1R_BASE	0xFE965140
+#define MEDIA_AXI_FDP1W_BASE	0xFE967140
+#define MEDIA_AXI_IMRR_BASE	0xFE965180
+#define MEDIA_AXI_IMRW_BASE	0xFE967180
+#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
+#define MEDIA_AXI_VPC0R_BASE	0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
+
+#define SYS_AXI_AVBDMSCR	0xFF802000
+#define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_CC50DMSCR	0xFF802008
+#define SYS_AXI_CC51DMSCR	0xFF80200C
+#define SYS_AXI_CCIDMSCR	0xFF802010
+#define SYS_AXI_CSDMSCR		0xFF802014
+#define SYS_AXI_DDMDMSCR	0xFF802018
+#define SYS_AXI_ETHDMSCR	0xFF80201C
+#define SYS_AXI_G2DDMSCR	0xFF802020
+#define SYS_AXI_IMP0DMSCR	0xFF802024
+#define SYS_AXI_IMP1DMSCR	0xFF802028
+#define SYS_AXI_LBSDMSCR	0xFF80202C
+#define SYS_AXI_MMUDSDMSCR	0xFF802030
+#define SYS_AXI_MMUMXDMSCR	0xFF802034
+#define SYS_AXI_MMURDDMSCR	0xFF802038
+#define SYS_AXI_MMUS0DMSCR	0xFF80203C
+#define SYS_AXI_MMUS1DMSCR	0xFF802040
+#define SYS_AXI_MPXDMSCR	0xFF802044
+#define SYS_AXI_MTSB0DMSCR	0xFF802048
+#define SYS_AXI_MTSB1DMSCR	0xFF80204C
+#define SYS_AXI_PCIDMSCR	0xFF802050
+#define SYS_AXI_RTXDMSCR	0xFF802054
+#define SYS_AXI_SAT0DMSCR	0xFF802058
+#define SYS_AXI_SAT1DMSCR	0xFF80205C
+#define SYS_AXI_SDM0DMSCR	0xFF802060
+#define SYS_AXI_SDM1DMSCR	0xFF802064
+#define SYS_AXI_SDS0DMSCR	0xFF802068
+#define SYS_AXI_SDS1DMSCR	0xFF80206C
+#define SYS_AXI_ETRABDMSCR	0xFF802070
+#define SYS_AXI_ETRKFDMSCR	0xFF802074
+#define SYS_AXI_UDM0DMSCR	0xFF802078
+#define SYS_AXI_UDM1DMSCR	0xFF80207C
+#define SYS_AXI_USB20DMSCR	0xFF802080
+#define SYS_AXI_USB21DMSCR	0xFF802084
+#define SYS_AXI_USB22DMSCR	0xFF802088
+#define SYS_AXI_USB30DMSCR	0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
+#define SYS_AXI_AVBSLVDMSCR	0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR	0xFF802110
+#define SYS_AXI_GICSLVDMSCR	0xFF802114
+#define SYS_AXI_IMPSLVDMSCR	0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
+#define SYS_AXI_LBSSLVDMSCR	0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
+#define SYS_AXI_MPXSLVDMSCR	0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR	0xFF802140
+#define SYS_AXI_PCISLVDMSCR	0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_STBSLVDMSCR	0xFF802188
+#define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+
+#define RT_AXI_CBMDMSCR		0xFF812000
+#define RT_AXI_DBDMSCR		0xFF812004
+#define RT_AXI_RDMDMSCR		0xFF812008
+#define RT_AXI_RDSDMSCR		0xFF81200C
+#define RT_AXI_STRDMSCR		0xFF812010
+#define RT_AXI_SY2RTDMSCR	0xFF812014
+#define RT_AXI_CBSSLVDMSCR	0xFF812100
+#define RT_AXI_DBSSLVDMSCR	0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
+
+#define MP_AXI_ADSPDMSCR	0xFF822000
+#define MP_AXI_ASDM0DMSCR	0xFF822004
+#define MP_AXI_ASDM1DMSCR	0xFF822008
+#define MP_AXI_ASDS0DMSCR	0xFF82200C
+#define MP_AXI_ASDS1DMSCR	0xFF822010
+#define MP_AXI_MLPDMSCR		0xFF822014
+#define MP_AXI_MMUMPDMSCR	0xFF822018
+#define MP_AXI_SPUDMSCR		0xFF82201C
+#define MP_AXI_SPUCDMSCR	0xFF822020
+#define MP_AXI_SY2MPDMSCR	0xFF822024
+#define MP_AXI_ADSPSLVDMSCR	0xFF822100
+#define MP_AXI_MLMSLVDMSCR	0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
+#define MP_AXI_SPUSLVDMSCR	0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR	0xFF842000
+#define ADM_AXI_ASDM1DMSCR	0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
+
+#define DM_AXI_RDMDMSCR		0xFF852000
+#define DM_AXI_SDM0DMSCR	0xFF852004
+#define DM_AXI_SDM1DMSCR	0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
+#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR	0xFF852110
+#define DM_AXI_SAP4SLVDMSCR	0xFF852114
+#define DM_AXI_SAP5SLVDMSCR	0xFF852118
+#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR	0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+
+#define SYS_AXI256_SYXDMSCR	0xFF862000
+#define SYS_AXI256_MPXDMSCR	0xFF862004
+#define SYS_AXI256_MXIDMSCR	0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
+
+#define MXT_SYXDMSCR		0xFF872000
+#define MXT_CMM0SLVDMSCR	0xFF872100
+#define MXT_CMM1SLVDMSCR	0xFF872104
+#define MXT_CMM2SLVDMSCR	0xFF872108
+#define MXT_FDPSLVDMSCR		0xFF87210C
+#define MXT_IMRSLVDMSCR		0xFF872110
+#define MXT_VINSLVDMSCR		0xFF872114
+#define MXT_VPC0SLVDMSCR	0xFF872118
+#define MXT_VPC1SLVDMSCR	0xFF87211C
+#define MXT_VSP0SLVDMSCR	0xFF872120
+#define MXT_VSP1SLVDMSCR	0xFF872124
+#define MXT_VSPD0SLVDMSCR	0xFF872128
+#define MXT_VSPD1SLVDMSCR	0xFF87212C
+#define MXT_MAP1SLVDMSCR	0xFF872130
+#define MXT_MAP2SLVDMSCR	0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR	0xFF882000
+#define CCI_AXI_SYX2DMSCR	0xFF882004
+#define CCI_AXI_MMURDMSCR	0xFF882008
+#define CCI_AXI_MMUDSDMSCR	0xFF88200C
+#define CCI_AXI_MMUMDMSCR	0xFF882010
+#define CCI_AXI_MXIDMSCR	0xFF882014
+#define CCI_AXI_MMUS1DMSCR	0xFF882018
+#define CCI_AXI_MMUMPDMSCR	0xFF88201C
+#define CCI_AXI_DVMDMSCR	0xFF882020
+#define CCI_AXI_CCISLVDMSCR	0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR	0xFF880400
+#define CCI_AXI_IPMMURDVMCR	0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
+#define CCI_AXI_AX2ADDRMASK	0xFF88041C
+
+#define PLL0CR			0xE61500D8
+#define PLL0_STC_MASK		0x7F000000
+#define PLL0_STC_BIT		24
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct rcar_rwdt {
+	u32 rwtcnt;	/* 0x00 */
+	u32 rwtcsra;	/* 0x04 */
+	u16 rwtcsrb;	/* 0x08 */
+};
+
+/* SWDT */
+struct rcar_swdt {
+	u32 swtcnt;	/* 0x00 */
+	u32 swtcsra;	/* 0x04 */
+	u16 swtcsrb;	/* 0x08 */
+};
+
+/* LBSC */
+struct rcar_lbsc {
+	u32 cs0ctrl;
+	u32 cs1ctrl;
+	u32 ecs0ctrl;
+	u32 ecs1ctrl;
+	u32 ecs2ctrl;
+	u32 ecs3ctrl;
+	u32 ecs4ctrl;
+	u32 ecs5ctrl;
+	u32 dummy0[4];	/* 0x20 .. 0x2C */
+	u32 cswcr0;
+	u32 cswcr1;
+	u32 ecswcr0;
+	u32 ecswcr1;
+	u32 ecswcr2;
+	u32 ecswcr3;
+	u32 ecswcr4;
+	u32 ecswcr5;
+	u32 exdmawcr0;
+	u32 exdmawcr1;
+	u32 exdmawcr2;
+	u32 dummy1[9];	/* 0x5C .. 0x7C */
+	u32 cspwcr0;
+	u32 cspwcr1;
+	u32 ecspwcr0;
+	u32 ecspwcr1;
+	u32 ecspwcr2;
+	u32 ecspwcr3;
+	u32 ecspwcr4;
+	u32 ecspwcr5;
+	u32 exwtsync;
+	u32 dummy2[3];	/* 0xA4 .. 0xAC */
+	u32 cs0bstctl;
+	u32 cs0btph;
+	u32 dummy3[2];	/* 0xB8 .. 0xBC */
+	u32 cs1gdst;
+	u32 ecs0gdst;
+	u32 ecs1gdst;
+	u32 ecs2gdst;
+	u32 ecs3gdst;
+	u32 ecs4gdst;
+	u32 ecs5gdst;
+	u32 dummy4[5];	/* 0xDC .. 0xEC */
+	u32 exdmaset0;
+	u32 exdmaset1;
+	u32 exdmaset2;
+	u32 dummy5[5];	/* 0xFC .. 0x10C */
+	u32 exdmcr0;
+	u32 exdmcr1;
+	u32 exdmcr2;
+	u32 dummy6[5];	/* 0x11C .. 0x12C */
+	u32 bcintsr;
+	u32 bcintcr;
+	u32 bcintmr;
+	u32 dummy7;	/* 0x13C */
+	u32 exbatlv;
+	u32 exwtsts;
+	u32 dummy8[14];	/* 0x148 .. 0x17C */
+	u32 atacsctrl;
+	u32 dummy9[15]; /* 0x184 .. 0x1BC */
+	u32 exbct;
+	u32 extct;
+};
+
+/* DBSC3 */
+struct rcar_dbsc3 {
+	u32 dummy0[3];	/* 0x00 .. 0x08 */
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2];	/* 0x28 .. 0x2C */
+	u32 dbphytype;
+	u32 dummy2[3];	/* 0x34 .. 0x3C */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3;	/* 0x4C */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7];	/* 0x94 .. 0xAC */
+	u32 dbbl;
+	u32 dummy5[3];	/* 0xB4 .. 0xBC */
+	u32 dbadj0;
+	u32 dummy6;	/* 0xC4 */
+	u32 dbadj2;
+	u32 dummy7[5];	/* 0xCC .. 0xDC */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dummy8[2];	/* 0xEC .. 0xF0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy9;	/* 0xFC */
+	u32 dbrnk0;
+	u32 dummy10[31];	/* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy11[47];	/* 0x184 ..0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[14];	/* 0x248 .. 0x27C */
+	u32 dbpdlck;
+	u32 dummy13[3];	/* 0x284 .. 0x28C */
+	u32 dbpdrga;
+	u32 dummy14[3];	/* 0x294 .. 0x29C */
+	u32 dbpdrgd;
+	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
+	u32 dbbs0cnt1;
+	u32 dummy16[30];	/* 0x308 .. 0x37C */
+	u32 dbwt0cnf0;
+	u32 dbwt0cnf1;
+	u32 dbwt0cnf2;
+	u32 dbwt0cnf3;
+	u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct rcar_gpio {
+	u32 iointsel;
+	u32 inoutsel;
+	u32 outdt;
+	u32 indt;
+	u32 intdt;
+	u32 intclr;
+	u32 intmsk;
+	u32 posneg;
+	u32 edglevel;
+	u32 filonoff;
+	u32 intmsks;
+	u32 mskclrs;
+	u32 outdtsel;
+	u32 outdth;
+	u32 outdtl;
+	u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct rcar_s3c {
+	u32 s3cexcladdmsk;
+	u32 s3cexclidmsk;
+	u32 s3cadsplcr;
+	u32 s3cmaar;
+	u32 s3carcr11;
+	u32 s3crorr;
+	u32 s3cworr;
+	u32 s3carcr22;
+	u32 dummy1[2];	/* 0x20 .. 0x24 */
+	u32 s3cmctr;
+	u32 dummy2;	/* 0x2C */
+	u32 cconf0;
+	u32 cconf1;
+	u32 cconf2;
+	u32 cconf3;
+};
+
+struct rcar_s3c_qos {
+	u32 s3cqos0;
+	u32 s3cqos1;
+	u32 s3cqos2;
+	u32 s3cqos3;
+	u32 s3cqos4;
+	u32 s3cqos5;
+	u32 s3cqos6;
+	u32 s3cqos7;
+	u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct rcar_dbsc3_qos {
+	u32 dblgcnt;
+	u32 dbtmval0;
+	u32 dbtmval1;
+	u32 dbtmval2;
+	u32 dbtmval3;
+	u32 dbrqctr;
+	u32 dbthres0;
+	u32 dbthres1;
+	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
+	u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct rcar_mxi {
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[7];	/* 0x08 .. 0x20 */
+	u32 mxaxiracr;	/* R8a7790 only */
+	u32 mxs3cracr;
+	u32 dummy1[2];	/* 0x2C .. 0x30 */
+	u32 mxaxiwacr;	/* R8a7790 only */
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
+	u32 mxrtcr;
+	u32 mxwtcr;
+};
+
+struct rcar_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
+/* AXI(QoS) */
+struct rcar_axi_qos {
+	u32 qosconf;
+	u32 qosctset0;
+	u32 qosctset1;
+	u32 qosctset2;
+	u32 qosctset3;
+	u32 qosreqctr;
+	u32 qosthres0;
+	u32 qosthres1;
+	u32 qosthres2;
+	u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_RCAR_BASE_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
index 2382565..ebddd7a 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -15,4 +15,10 @@
 #endif
 #endif /* CONFIG_RMOBILE */
 
+#ifndef __ASSEMBLY__
+u32 rmobile_get_cpu_type(void);
+u32 rmobile_get_cpu_rev_integer(void);
+u32 rmobile_get_cpu_rev_fraction(void);
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_ARCH_RMOBILE_H */
diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
index da8df74..d5dbc22 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h
@@ -19,170 +19,830 @@ struct s5p_gpio_bank {
 	unsigned char	res1[8];
 };
 
-struct s5pc100_gpio {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank b;
-	struct s5p_gpio_bank c;
-	struct s5p_gpio_bank d;
-	struct s5p_gpio_bank e0;
-	struct s5p_gpio_bank e1;
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank f2;
-	struct s5p_gpio_bank f3;
-	struct s5p_gpio_bank g0;
-	struct s5p_gpio_bank g1;
-	struct s5p_gpio_bank g2;
-	struct s5p_gpio_bank g3;
-	struct s5p_gpio_bank i;
-	struct s5p_gpio_bank j0;
-	struct s5p_gpio_bank j1;
-	struct s5p_gpio_bank j2;
-	struct s5p_gpio_bank j3;
-	struct s5p_gpio_bank j4;
-	struct s5p_gpio_bank k0;
-	struct s5p_gpio_bank k1;
-	struct s5p_gpio_bank k2;
-	struct s5p_gpio_bank k3;
-	struct s5p_gpio_bank l0;
-	struct s5p_gpio_bank l1;
-	struct s5p_gpio_bank l2;
-	struct s5p_gpio_bank l3;
-	struct s5p_gpio_bank l4;
-	struct s5p_gpio_bank h0;
-	struct s5p_gpio_bank h1;
-	struct s5p_gpio_bank h2;
-	struct s5p_gpio_bank h3;
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum s5pc100_gpio_pin {
+	S5PC100_GPIO_A00,
+	S5PC100_GPIO_A01,
+	S5PC100_GPIO_A02,
+	S5PC100_GPIO_A03,
+	S5PC100_GPIO_A04,
+	S5PC100_GPIO_A05,
+	S5PC100_GPIO_A06,
+	S5PC100_GPIO_A07,
+	S5PC100_GPIO_A10,
+	S5PC100_GPIO_A11,
+	S5PC100_GPIO_A12,
+	S5PC100_GPIO_A13,
+	S5PC100_GPIO_A14,
+	S5PC100_GPIO_A15,
+	S5PC100_GPIO_A16,
+	S5PC100_GPIO_A17,
+	S5PC100_GPIO_B0,
+	S5PC100_GPIO_B1,
+	S5PC100_GPIO_B2,
+	S5PC100_GPIO_B3,
+	S5PC100_GPIO_B4,
+	S5PC100_GPIO_B5,
+	S5PC100_GPIO_B6,
+	S5PC100_GPIO_B7,
+	S5PC100_GPIO_C0,
+	S5PC100_GPIO_C1,
+	S5PC100_GPIO_C2,
+	S5PC100_GPIO_C3,
+	S5PC100_GPIO_C4,
+	S5PC100_GPIO_C5,
+	S5PC100_GPIO_C6,
+	S5PC100_GPIO_C7,
+	S5PC100_GPIO_D0,
+	S5PC100_GPIO_D1,
+	S5PC100_GPIO_D2,
+	S5PC100_GPIO_D3,
+	S5PC100_GPIO_D4,
+	S5PC100_GPIO_D5,
+	S5PC100_GPIO_D6,
+	S5PC100_GPIO_D7,
+	S5PC100_GPIO_E00,
+	S5PC100_GPIO_E01,
+	S5PC100_GPIO_E02,
+	S5PC100_GPIO_E03,
+	S5PC100_GPIO_E04,
+	S5PC100_GPIO_E05,
+	S5PC100_GPIO_E06,
+	S5PC100_GPIO_E07,
+	S5PC100_GPIO_E10,
+	S5PC100_GPIO_E11,
+	S5PC100_GPIO_E12,
+	S5PC100_GPIO_E13,
+	S5PC100_GPIO_E14,
+	S5PC100_GPIO_E15,
+	S5PC100_GPIO_E16,
+	S5PC100_GPIO_E17,
+	S5PC100_GPIO_F00,
+	S5PC100_GPIO_F01,
+	S5PC100_GPIO_F02,
+	S5PC100_GPIO_F03,
+	S5PC100_GPIO_F04,
+	S5PC100_GPIO_F05,
+	S5PC100_GPIO_F06,
+	S5PC100_GPIO_F07,
+	S5PC100_GPIO_F10,
+	S5PC100_GPIO_F11,
+	S5PC100_GPIO_F12,
+	S5PC100_GPIO_F13,
+	S5PC100_GPIO_F14,
+	S5PC100_GPIO_F15,
+	S5PC100_GPIO_F16,
+	S5PC100_GPIO_F17,
+	S5PC100_GPIO_F20,
+	S5PC100_GPIO_F21,
+	S5PC100_GPIO_F22,
+	S5PC100_GPIO_F23,
+	S5PC100_GPIO_F24,
+	S5PC100_GPIO_F25,
+	S5PC100_GPIO_F26,
+	S5PC100_GPIO_F27,
+	S5PC100_GPIO_F30,
+	S5PC100_GPIO_F31,
+	S5PC100_GPIO_F32,
+	S5PC100_GPIO_F33,
+	S5PC100_GPIO_F34,
+	S5PC100_GPIO_F35,
+	S5PC100_GPIO_F36,
+	S5PC100_GPIO_F37,
+	S5PC100_GPIO_G00,
+	S5PC100_GPIO_G01,
+	S5PC100_GPIO_G02,
+	S5PC100_GPIO_G03,
+	S5PC100_GPIO_G04,
+	S5PC100_GPIO_G05,
+	S5PC100_GPIO_G06,
+	S5PC100_GPIO_G07,
+	S5PC100_GPIO_G10,
+	S5PC100_GPIO_G11,
+	S5PC100_GPIO_G12,
+	S5PC100_GPIO_G13,
+	S5PC100_GPIO_G14,
+	S5PC100_GPIO_G15,
+	S5PC100_GPIO_G16,
+	S5PC100_GPIO_G17,
+	S5PC100_GPIO_G20,
+	S5PC100_GPIO_G21,
+	S5PC100_GPIO_G22,
+	S5PC100_GPIO_G23,
+	S5PC100_GPIO_G24,
+	S5PC100_GPIO_G25,
+	S5PC100_GPIO_G26,
+	S5PC100_GPIO_G27,
+	S5PC100_GPIO_G30,
+	S5PC100_GPIO_G31,
+	S5PC100_GPIO_G32,
+	S5PC100_GPIO_G33,
+	S5PC100_GPIO_G34,
+	S5PC100_GPIO_G35,
+	S5PC100_GPIO_G36,
+	S5PC100_GPIO_G37,
+	S5PC100_GPIO_I0,
+	S5PC100_GPIO_I1,
+	S5PC100_GPIO_I2,
+	S5PC100_GPIO_I3,
+	S5PC100_GPIO_I4,
+	S5PC100_GPIO_I5,
+	S5PC100_GPIO_I6,
+	S5PC100_GPIO_I7,
+	S5PC100_GPIO_J00,
+	S5PC100_GPIO_J01,
+	S5PC100_GPIO_J02,
+	S5PC100_GPIO_J03,
+	S5PC100_GPIO_J04,
+	S5PC100_GPIO_J05,
+	S5PC100_GPIO_J06,
+	S5PC100_GPIO_J07,
+	S5PC100_GPIO_J10,
+	S5PC100_GPIO_J11,
+	S5PC100_GPIO_J12,
+	S5PC100_GPIO_J13,
+	S5PC100_GPIO_J14,
+	S5PC100_GPIO_J15,
+	S5PC100_GPIO_J16,
+	S5PC100_GPIO_J17,
+	S5PC100_GPIO_J20,
+	S5PC100_GPIO_J21,
+	S5PC100_GPIO_J22,
+	S5PC100_GPIO_J23,
+	S5PC100_GPIO_J24,
+	S5PC100_GPIO_J25,
+	S5PC100_GPIO_J26,
+	S5PC100_GPIO_J27,
+	S5PC100_GPIO_J30,
+	S5PC100_GPIO_J31,
+	S5PC100_GPIO_J32,
+	S5PC100_GPIO_J33,
+	S5PC100_GPIO_J34,
+	S5PC100_GPIO_J35,
+	S5PC100_GPIO_J36,
+	S5PC100_GPIO_J37,
+	S5PC100_GPIO_J40,
+	S5PC100_GPIO_J41,
+	S5PC100_GPIO_J42,
+	S5PC100_GPIO_J43,
+	S5PC100_GPIO_J44,
+	S5PC100_GPIO_J45,
+	S5PC100_GPIO_J46,
+	S5PC100_GPIO_J47,
+	S5PC100_GPIO_K00,
+	S5PC100_GPIO_K01,
+	S5PC100_GPIO_K02,
+	S5PC100_GPIO_K03,
+	S5PC100_GPIO_K04,
+	S5PC100_GPIO_K05,
+	S5PC100_GPIO_K06,
+	S5PC100_GPIO_K07,
+	S5PC100_GPIO_K10,
+	S5PC100_GPIO_K11,
+	S5PC100_GPIO_K12,
+	S5PC100_GPIO_K13,
+	S5PC100_GPIO_K14,
+	S5PC100_GPIO_K15,
+	S5PC100_GPIO_K16,
+	S5PC100_GPIO_K17,
+	S5PC100_GPIO_K20,
+	S5PC100_GPIO_K21,
+	S5PC100_GPIO_K22,
+	S5PC100_GPIO_K23,
+	S5PC100_GPIO_K24,
+	S5PC100_GPIO_K25,
+	S5PC100_GPIO_K26,
+	S5PC100_GPIO_K27,
+	S5PC100_GPIO_K30,
+	S5PC100_GPIO_K31,
+	S5PC100_GPIO_K32,
+	S5PC100_GPIO_K33,
+	S5PC100_GPIO_K34,
+	S5PC100_GPIO_K35,
+	S5PC100_GPIO_K36,
+	S5PC100_GPIO_K37,
+	S5PC100_GPIO_L00,
+	S5PC100_GPIO_L01,
+	S5PC100_GPIO_L02,
+	S5PC100_GPIO_L03,
+	S5PC100_GPIO_L04,
+	S5PC100_GPIO_L05,
+	S5PC100_GPIO_L06,
+	S5PC100_GPIO_L07,
+	S5PC100_GPIO_L10,
+	S5PC100_GPIO_L11,
+	S5PC100_GPIO_L12,
+	S5PC100_GPIO_L13,
+	S5PC100_GPIO_L14,
+	S5PC100_GPIO_L15,
+	S5PC100_GPIO_L16,
+	S5PC100_GPIO_L17,
+	S5PC100_GPIO_L20,
+	S5PC100_GPIO_L21,
+	S5PC100_GPIO_L22,
+	S5PC100_GPIO_L23,
+	S5PC100_GPIO_L24,
+	S5PC100_GPIO_L25,
+	S5PC100_GPIO_L26,
+	S5PC100_GPIO_L27,
+	S5PC100_GPIO_L30,
+	S5PC100_GPIO_L31,
+	S5PC100_GPIO_L32,
+	S5PC100_GPIO_L33,
+	S5PC100_GPIO_L34,
+	S5PC100_GPIO_L35,
+	S5PC100_GPIO_L36,
+	S5PC100_GPIO_L37,
+	S5PC100_GPIO_L40,
+	S5PC100_GPIO_L41,
+	S5PC100_GPIO_L42,
+	S5PC100_GPIO_L43,
+	S5PC100_GPIO_L44,
+	S5PC100_GPIO_L45,
+	S5PC100_GPIO_L46,
+	S5PC100_GPIO_L47,
+	S5PC100_GPIO_H00,
+	S5PC100_GPIO_H01,
+	S5PC100_GPIO_H02,
+	S5PC100_GPIO_H03,
+	S5PC100_GPIO_H04,
+	S5PC100_GPIO_H05,
+	S5PC100_GPIO_H06,
+	S5PC100_GPIO_H07,
+	S5PC100_GPIO_H10,
+	S5PC100_GPIO_H11,
+	S5PC100_GPIO_H12,
+	S5PC100_GPIO_H13,
+	S5PC100_GPIO_H14,
+	S5PC100_GPIO_H15,
+	S5PC100_GPIO_H16,
+	S5PC100_GPIO_H17,
+	S5PC100_GPIO_H20,
+	S5PC100_GPIO_H21,
+	S5PC100_GPIO_H22,
+	S5PC100_GPIO_H23,
+	S5PC100_GPIO_H24,
+	S5PC100_GPIO_H25,
+	S5PC100_GPIO_H26,
+	S5PC100_GPIO_H27,
+	S5PC100_GPIO_H30,
+	S5PC100_GPIO_H31,
+	S5PC100_GPIO_H32,
+	S5PC100_GPIO_H33,
+	S5PC100_GPIO_H34,
+	S5PC100_GPIO_H35,
+	S5PC100_GPIO_H36,
+	S5PC100_GPIO_H37,
+
+	S5PC100_GPIO_MAX_PORT
 };
 
-struct s5pc110_gpio {
-	struct s5p_gpio_bank a0;
-	struct s5p_gpio_bank a1;
-	struct s5p_gpio_bank b;
-	struct s5p_gpio_bank c0;
-	struct s5p_gpio_bank c1;
-	struct s5p_gpio_bank d0;
-	struct s5p_gpio_bank d1;
-	struct s5p_gpio_bank e0;
-	struct s5p_gpio_bank e1;
-	struct s5p_gpio_bank f0;
-	struct s5p_gpio_bank f1;
-	struct s5p_gpio_bank f2;
-	struct s5p_gpio_bank f3;
-	struct s5p_gpio_bank g0;
-	struct s5p_gpio_bank g1;
-	struct s5p_gpio_bank g2;
-	struct s5p_gpio_bank g3;
-	struct s5p_gpio_bank i;
-	struct s5p_gpio_bank j0;
-	struct s5p_gpio_bank j1;
-	struct s5p_gpio_bank j2;
-	struct s5p_gpio_bank j3;
-	struct s5p_gpio_bank j4;
-	struct s5p_gpio_bank mp0_1;
-	struct s5p_gpio_bank mp0_2;
-	struct s5p_gpio_bank mp0_3;
-	struct s5p_gpio_bank mp0_4;
-	struct s5p_gpio_bank mp0_5;
-	struct s5p_gpio_bank mp0_6;
-	struct s5p_gpio_bank mp0_7;
-	struct s5p_gpio_bank mp1_0;
-	struct s5p_gpio_bank mp1_1;
-	struct s5p_gpio_bank mp1_2;
-	struct s5p_gpio_bank mp1_3;
-	struct s5p_gpio_bank mp1_4;
-	struct s5p_gpio_bank mp1_5;
-	struct s5p_gpio_bank mp1_6;
-	struct s5p_gpio_bank mp1_7;
-	struct s5p_gpio_bank mp1_8;
-	struct s5p_gpio_bank mp2_0;
-	struct s5p_gpio_bank mp2_1;
-	struct s5p_gpio_bank mp2_2;
-	struct s5p_gpio_bank mp2_3;
-	struct s5p_gpio_bank mp2_4;
-	struct s5p_gpio_bank mp2_5;
-	struct s5p_gpio_bank mp2_6;
-	struct s5p_gpio_bank mp2_7;
-	struct s5p_gpio_bank mp2_8;
-	struct s5p_gpio_bank res1[48];
-	struct s5p_gpio_bank h0;
-	struct s5p_gpio_bank h1;
-	struct s5p_gpio_bank h2;
-	struct s5p_gpio_bank h3;
+enum s5pc110_gpio_pin {
+	S5PC110_GPIO_A00,
+	S5PC110_GPIO_A01,
+	S5PC110_GPIO_A02,
+	S5PC110_GPIO_A03,
+	S5PC110_GPIO_A04,
+	S5PC110_GPIO_A05,
+	S5PC110_GPIO_A06,
+	S5PC110_GPIO_A07,
+	S5PC110_GPIO_A10,
+	S5PC110_GPIO_A11,
+	S5PC110_GPIO_A12,
+	S5PC110_GPIO_A13,
+	S5PC110_GPIO_A14,
+	S5PC110_GPIO_A15,
+	S5PC110_GPIO_A16,
+	S5PC110_GPIO_A17,
+	S5PC110_GPIO_B0,
+	S5PC110_GPIO_B1,
+	S5PC110_GPIO_B2,
+	S5PC110_GPIO_B3,
+	S5PC110_GPIO_B4,
+	S5PC110_GPIO_B5,
+	S5PC110_GPIO_B6,
+	S5PC110_GPIO_B7,
+	S5PC110_GPIO_C00,
+	S5PC110_GPIO_C01,
+	S5PC110_GPIO_C02,
+	S5PC110_GPIO_C03,
+	S5PC110_GPIO_C04,
+	S5PC110_GPIO_C05,
+	S5PC110_GPIO_C06,
+	S5PC110_GPIO_C07,
+	S5PC110_GPIO_C10,
+	S5PC110_GPIO_C11,
+	S5PC110_GPIO_C12,
+	S5PC110_GPIO_C13,
+	S5PC110_GPIO_C14,
+	S5PC110_GPIO_C15,
+	S5PC110_GPIO_C16,
+	S5PC110_GPIO_C17,
+	S5PC110_GPIO_D00,
+	S5PC110_GPIO_D01,
+	S5PC110_GPIO_D02,
+	S5PC110_GPIO_D03,
+	S5PC110_GPIO_D04,
+	S5PC110_GPIO_D05,
+	S5PC110_GPIO_D06,
+	S5PC110_GPIO_D07,
+	S5PC110_GPIO_D10,
+	S5PC110_GPIO_D11,
+	S5PC110_GPIO_D12,
+	S5PC110_GPIO_D13,
+	S5PC110_GPIO_D14,
+	S5PC110_GPIO_D15,
+	S5PC110_GPIO_D16,
+	S5PC110_GPIO_D17,
+	S5PC110_GPIO_E00,
+	S5PC110_GPIO_E01,
+	S5PC110_GPIO_E02,
+	S5PC110_GPIO_E03,
+	S5PC110_GPIO_E04,
+	S5PC110_GPIO_E05,
+	S5PC110_GPIO_E06,
+	S5PC110_GPIO_E07,
+	S5PC110_GPIO_E10,
+	S5PC110_GPIO_E11,
+	S5PC110_GPIO_E12,
+	S5PC110_GPIO_E13,
+	S5PC110_GPIO_E14,
+	S5PC110_GPIO_E15,
+	S5PC110_GPIO_E16,
+	S5PC110_GPIO_E17,
+	S5PC110_GPIO_F00,
+	S5PC110_GPIO_F01,
+	S5PC110_GPIO_F02,
+	S5PC110_GPIO_F03,
+	S5PC110_GPIO_F04,
+	S5PC110_GPIO_F05,
+	S5PC110_GPIO_F06,
+	S5PC110_GPIO_F07,
+	S5PC110_GPIO_F10,
+	S5PC110_GPIO_F11,
+	S5PC110_GPIO_F12,
+	S5PC110_GPIO_F13,
+	S5PC110_GPIO_F14,
+	S5PC110_GPIO_F15,
+	S5PC110_GPIO_F16,
+	S5PC110_GPIO_F17,
+	S5PC110_GPIO_F20,
+	S5PC110_GPIO_F21,
+	S5PC110_GPIO_F22,
+	S5PC110_GPIO_F23,
+	S5PC110_GPIO_F24,
+	S5PC110_GPIO_F25,
+	S5PC110_GPIO_F26,
+	S5PC110_GPIO_F27,
+	S5PC110_GPIO_F30,
+	S5PC110_GPIO_F31,
+	S5PC110_GPIO_F32,
+	S5PC110_GPIO_F33,
+	S5PC110_GPIO_F34,
+	S5PC110_GPIO_F35,
+	S5PC110_GPIO_F36,
+	S5PC110_GPIO_F37,
+	S5PC110_GPIO_G00,
+	S5PC110_GPIO_G01,
+	S5PC110_GPIO_G02,
+	S5PC110_GPIO_G03,
+	S5PC110_GPIO_G04,
+	S5PC110_GPIO_G05,
+	S5PC110_GPIO_G06,
+	S5PC110_GPIO_G07,
+	S5PC110_GPIO_G10,
+	S5PC110_GPIO_G11,
+	S5PC110_GPIO_G12,
+	S5PC110_GPIO_G13,
+	S5PC110_GPIO_G14,
+	S5PC110_GPIO_G15,
+	S5PC110_GPIO_G16,
+	S5PC110_GPIO_G17,
+	S5PC110_GPIO_G20,
+	S5PC110_GPIO_G21,
+	S5PC110_GPIO_G22,
+	S5PC110_GPIO_G23,
+	S5PC110_GPIO_G24,
+	S5PC110_GPIO_G25,
+	S5PC110_GPIO_G26,
+	S5PC110_GPIO_G27,
+	S5PC110_GPIO_G30,
+	S5PC110_GPIO_G31,
+	S5PC110_GPIO_G32,
+	S5PC110_GPIO_G33,
+	S5PC110_GPIO_G34,
+	S5PC110_GPIO_G35,
+	S5PC110_GPIO_G36,
+	S5PC110_GPIO_G37,
+	S5PC110_GPIO_I0,
+	S5PC110_GPIO_I1,
+	S5PC110_GPIO_I2,
+	S5PC110_GPIO_I3,
+	S5PC110_GPIO_I4,
+	S5PC110_GPIO_I5,
+	S5PC110_GPIO_I6,
+	S5PC110_GPIO_I7,
+	S5PC110_GPIO_J00,
+	S5PC110_GPIO_J01,
+	S5PC110_GPIO_J02,
+	S5PC110_GPIO_J03,
+	S5PC110_GPIO_J04,
+	S5PC110_GPIO_J05,
+	S5PC110_GPIO_J06,
+	S5PC110_GPIO_J07,
+	S5PC110_GPIO_J10,
+	S5PC110_GPIO_J11,
+	S5PC110_GPIO_J12,
+	S5PC110_GPIO_J13,
+	S5PC110_GPIO_J14,
+	S5PC110_GPIO_J15,
+	S5PC110_GPIO_J16,
+	S5PC110_GPIO_J17,
+	S5PC110_GPIO_J20,
+	S5PC110_GPIO_J21,
+	S5PC110_GPIO_J22,
+	S5PC110_GPIO_J23,
+	S5PC110_GPIO_J24,
+	S5PC110_GPIO_J25,
+	S5PC110_GPIO_J26,
+	S5PC110_GPIO_J27,
+	S5PC110_GPIO_J30,
+	S5PC110_GPIO_J31,
+	S5PC110_GPIO_J32,
+	S5PC110_GPIO_J33,
+	S5PC110_GPIO_J34,
+	S5PC110_GPIO_J35,
+	S5PC110_GPIO_J36,
+	S5PC110_GPIO_J37,
+	S5PC110_GPIO_J40,
+	S5PC110_GPIO_J41,
+	S5PC110_GPIO_J42,
+	S5PC110_GPIO_J43,
+	S5PC110_GPIO_J44,
+	S5PC110_GPIO_J45,
+	S5PC110_GPIO_J46,
+	S5PC110_GPIO_J47,
+	S5PC110_GPIO_MP010,
+	S5PC110_GPIO_MP011,
+	S5PC110_GPIO_MP012,
+	S5PC110_GPIO_MP013,
+	S5PC110_GPIO_MP014,
+	S5PC110_GPIO_MP015,
+	S5PC110_GPIO_MP016,
+	S5PC110_GPIO_MP017,
+	S5PC110_GPIO_MP020,
+	S5PC110_GPIO_MP021,
+	S5PC110_GPIO_MP022,
+	S5PC110_GPIO_MP023,
+	S5PC110_GPIO_MP024,
+	S5PC110_GPIO_MP025,
+	S5PC110_GPIO_MP026,
+	S5PC110_GPIO_MP027,
+	S5PC110_GPIO_MP030,
+	S5PC110_GPIO_MP031,
+	S5PC110_GPIO_MP032,
+	S5PC110_GPIO_MP033,
+	S5PC110_GPIO_MP034,
+	S5PC110_GPIO_MP035,
+	S5PC110_GPIO_MP036,
+	S5PC110_GPIO_MP037,
+	S5PC110_GPIO_MP040,
+	S5PC110_GPIO_MP041,
+	S5PC110_GPIO_MP042,
+	S5PC110_GPIO_MP043,
+	S5PC110_GPIO_MP044,
+	S5PC110_GPIO_MP045,
+	S5PC110_GPIO_MP046,
+	S5PC110_GPIO_MP047,
+	S5PC110_GPIO_MP050,
+	S5PC110_GPIO_MP051,
+	S5PC110_GPIO_MP052,
+	S5PC110_GPIO_MP053,
+	S5PC110_GPIO_MP054,
+	S5PC110_GPIO_MP055,
+	S5PC110_GPIO_MP056,
+	S5PC110_GPIO_MP057,
+	S5PC110_GPIO_MP060,
+	S5PC110_GPIO_MP061,
+	S5PC110_GPIO_MP062,
+	S5PC110_GPIO_MP063,
+	S5PC110_GPIO_MP064,
+	S5PC110_GPIO_MP065,
+	S5PC110_GPIO_MP066,
+	S5PC110_GPIO_MP067,
+	S5PC110_GPIO_MP070,
+	S5PC110_GPIO_MP071,
+	S5PC110_GPIO_MP072,
+	S5PC110_GPIO_MP073,
+	S5PC110_GPIO_MP074,
+	S5PC110_GPIO_MP075,
+	S5PC110_GPIO_MP076,
+	S5PC110_GPIO_MP077,
+	S5PC110_GPIO_MP100,
+	S5PC110_GPIO_MP101,
+	S5PC110_GPIO_MP102,
+	S5PC110_GPIO_MP103,
+	S5PC110_GPIO_MP104,
+	S5PC110_GPIO_MP105,
+	S5PC110_GPIO_MP106,
+	S5PC110_GPIO_MP107,
+	S5PC110_GPIO_MP110,
+	S5PC110_GPIO_MP111,
+	S5PC110_GPIO_MP112,
+	S5PC110_GPIO_MP113,
+	S5PC110_GPIO_MP114,
+	S5PC110_GPIO_MP115,
+	S5PC110_GPIO_MP116,
+	S5PC110_GPIO_MP117,
+	S5PC110_GPIO_MP120,
+	S5PC110_GPIO_MP121,
+	S5PC110_GPIO_MP122,
+	S5PC110_GPIO_MP123,
+	S5PC110_GPIO_MP124,
+	S5PC110_GPIO_MP125,
+	S5PC110_GPIO_MP126,
+	S5PC110_GPIO_MP127,
+	S5PC110_GPIO_MP130,
+	S5PC110_GPIO_MP131,
+	S5PC110_GPIO_MP132,
+	S5PC110_GPIO_MP133,
+	S5PC110_GPIO_MP134,
+	S5PC110_GPIO_MP135,
+	S5PC110_GPIO_MP136,
+	S5PC110_GPIO_MP137,
+	S5PC110_GPIO_MP140,
+	S5PC110_GPIO_MP141,
+	S5PC110_GPIO_MP142,
+	S5PC110_GPIO_MP143,
+	S5PC110_GPIO_MP144,
+	S5PC110_GPIO_MP145,
+	S5PC110_GPIO_MP146,
+	S5PC110_GPIO_MP147,
+	S5PC110_GPIO_MP150,
+	S5PC110_GPIO_MP151,
+	S5PC110_GPIO_MP152,
+	S5PC110_GPIO_MP153,
+	S5PC110_GPIO_MP154,
+	S5PC110_GPIO_MP155,
+	S5PC110_GPIO_MP156,
+	S5PC110_GPIO_MP157,
+	S5PC110_GPIO_MP160,
+	S5PC110_GPIO_MP161,
+	S5PC110_GPIO_MP162,
+	S5PC110_GPIO_MP163,
+	S5PC110_GPIO_MP164,
+	S5PC110_GPIO_MP165,
+	S5PC110_GPIO_MP166,
+	S5PC110_GPIO_MP167,
+	S5PC110_GPIO_MP170,
+	S5PC110_GPIO_MP171,
+	S5PC110_GPIO_MP172,
+	S5PC110_GPIO_MP173,
+	S5PC110_GPIO_MP174,
+	S5PC110_GPIO_MP175,
+	S5PC110_GPIO_MP176,
+	S5PC110_GPIO_MP177,
+	S5PC110_GPIO_MP180,
+	S5PC110_GPIO_MP181,
+	S5PC110_GPIO_MP182,
+	S5PC110_GPIO_MP183,
+	S5PC110_GPIO_MP184,
+	S5PC110_GPIO_MP185,
+	S5PC110_GPIO_MP186,
+	S5PC110_GPIO_MP187,
+	S5PC110_GPIO_MP200,
+	S5PC110_GPIO_MP201,
+	S5PC110_GPIO_MP202,
+	S5PC110_GPIO_MP203,
+	S5PC110_GPIO_MP204,
+	S5PC110_GPIO_MP205,
+	S5PC110_GPIO_MP206,
+	S5PC110_GPIO_MP207,
+	S5PC110_GPIO_MP210,
+	S5PC110_GPIO_MP211,
+	S5PC110_GPIO_MP212,
+	S5PC110_GPIO_MP213,
+	S5PC110_GPIO_MP214,
+	S5PC110_GPIO_MP215,
+	S5PC110_GPIO_MP216,
+	S5PC110_GPIO_MP217,
+	S5PC110_GPIO_MP220,
+	S5PC110_GPIO_MP221,
+	S5PC110_GPIO_MP222,
+	S5PC110_GPIO_MP223,
+	S5PC110_GPIO_MP224,
+	S5PC110_GPIO_MP225,
+	S5PC110_GPIO_MP226,
+	S5PC110_GPIO_MP227,
+	S5PC110_GPIO_MP230,
+	S5PC110_GPIO_MP231,
+	S5PC110_GPIO_MP232,
+	S5PC110_GPIO_MP233,
+	S5PC110_GPIO_MP234,
+	S5PC110_GPIO_MP235,
+	S5PC110_GPIO_MP236,
+	S5PC110_GPIO_MP237,
+	S5PC110_GPIO_MP240,
+	S5PC110_GPIO_MP241,
+	S5PC110_GPIO_MP242,
+	S5PC110_GPIO_MP243,
+	S5PC110_GPIO_MP244,
+	S5PC110_GPIO_MP245,
+	S5PC110_GPIO_MP246,
+	S5PC110_GPIO_MP247,
+	S5PC110_GPIO_MP250,
+	S5PC110_GPIO_MP251,
+	S5PC110_GPIO_MP252,
+	S5PC110_GPIO_MP253,
+	S5PC110_GPIO_MP254,
+	S5PC110_GPIO_MP255,
+	S5PC110_GPIO_MP256,
+	S5PC110_GPIO_MP257,
+	S5PC110_GPIO_MP260,
+	S5PC110_GPIO_MP261,
+	S5PC110_GPIO_MP262,
+	S5PC110_GPIO_MP263,
+	S5PC110_GPIO_MP264,
+	S5PC110_GPIO_MP265,
+	S5PC110_GPIO_MP266,
+	S5PC110_GPIO_MP267,
+	S5PC110_GPIO_MP270,
+	S5PC110_GPIO_MP271,
+	S5PC110_GPIO_MP272,
+	S5PC110_GPIO_MP273,
+	S5PC110_GPIO_MP274,
+	S5PC110_GPIO_MP275,
+	S5PC110_GPIO_MP276,
+	S5PC110_GPIO_MP277,
+	S5PC110_GPIO_MP280,
+	S5PC110_GPIO_MP281,
+	S5PC110_GPIO_MP282,
+	S5PC110_GPIO_MP283,
+	S5PC110_GPIO_MP284,
+	S5PC110_GPIO_MP285,
+	S5PC110_GPIO_MP286,
+	S5PC110_GPIO_MP287,
+	S5PC110_GPIO_RES,
+	S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)),
+	S5PC110_GPIO_H01,
+	S5PC110_GPIO_H02,
+	S5PC110_GPIO_H03,
+	S5PC110_GPIO_H04,
+	S5PC110_GPIO_H05,
+	S5PC110_GPIO_H06,
+	S5PC110_GPIO_H07,
+	S5PC110_GPIO_H10,
+	S5PC110_GPIO_H11,
+	S5PC110_GPIO_H12,
+	S5PC110_GPIO_H13,
+	S5PC110_GPIO_H14,
+	S5PC110_GPIO_H15,
+	S5PC110_GPIO_H16,
+	S5PC110_GPIO_H17,
+	S5PC110_GPIO_H20,
+	S5PC110_GPIO_H21,
+	S5PC110_GPIO_H22,
+	S5PC110_GPIO_H23,
+	S5PC110_GPIO_H24,
+	S5PC110_GPIO_H25,
+	S5PC110_GPIO_H26,
+	S5PC110_GPIO_H27,
+	S5PC110_GPIO_H30,
+	S5PC110_GPIO_H31,
+	S5PC110_GPIO_H32,
+	S5PC110_GPIO_H33,
+	S5PC110_GPIO_H34,
+	S5PC110_GPIO_H35,
+	S5PC110_GPIO_H36,
+	S5PC110_GPIO_H37,
+
+	S5PC110_GPIO_MAX_PORT
 };
 
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+struct gpio_info {
+	unsigned int reg_addr;	/* Address of register for this part */
+	unsigned int max_gpio;	/* Maximum GPIO in this part */
+};
 
-/* GPIO pins per bank  */
-#define GPIO_PER_BANK 8
+#define S5PC100_GPIO_NUM_PARTS	1
+static struct gpio_info s5pc100_gpio_data[S5PC100_GPIO_NUM_PARTS] = {
+	{ S5PC100_GPIO_BASE, S5PC100_GPIO_MAX_PORT },
+};
 
-#define S5P_GPIO_PART_SHIFT	(24)
-#define S5P_GPIO_PART_MASK	(0xff)
-#define S5P_GPIO_BANK_SHIFT	(8)
-#define S5P_GPIO_BANK_MASK	(0xffff)
-#define S5P_GPIO_PIN_MASK	(0xff)
+#define S5PC110_GPIO_NUM_PARTS	1
+static struct gpio_info s5pc110_gpio_data[S5PC110_GPIO_NUM_PARTS] = {
+	{ S5PC110_GPIO_BASE, S5PC110_GPIO_MAX_PORT },
+};
 
-#define S5P_GPIO_SET_PART(x) \
-			(((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT)
+static inline struct gpio_info *get_gpio_data(void)
+{
+	if (cpu_is_s5pc100())
+		return s5pc100_gpio_data;
+	else if (cpu_is_s5pc110())
+		return s5pc110_gpio_data;
 
-#define S5P_GPIO_GET_PART(x) \
-			(((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK)
+	return NULL;
+}
 
-#define S5P_GPIO_SET_PIN(x) \
-			((x) & S5P_GPIO_PIN_MASK)
+static inline unsigned int get_bank_num(void)
+{
+	if (cpu_is_s5pc100())
+		return S5PC100_GPIO_NUM_PARTS;
+	else if (cpu_is_s5pc110())
+		return S5PC110_GPIO_NUM_PARTS;
 
-#define S5PC100_SET_BANK(bank) \
-			(((unsigned)&(((struct s5pc100_gpio *) \
-			S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+	return 0;
+}
 
-#define S5PC110_SET_BANK(bank) \
-			((((unsigned)&(((struct s5pc110_gpio *) \
-			S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \
-			& S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT)
+/*
+ * This structure helps mapping symbolic GPIO names into indices from
+ * exynos5_gpio_pin/exynos5420_gpio_pin enums.
+ *
+ * By convention, symbolic GPIO name is defined as follows:
+ *
+ * g[p]<bank><set><bit>, where
+ *   p is optional
+ *   <bank> - a single character bank name, as defined by the SOC
+ *   <set> - a single digit set number
+ *   <bit> - bit number within the set (in 0..7 range).
+ *
+ * <set><bit> essentially form an octal number of the GPIO pin within the bank
+ * space. On the 5420 architecture some banks' sets do not start not from zero
+ * ('d' starts from 1 and 'j' starts from 4). To compensate for that and
+ * maintain flat number space withoout holes, those banks use offsets to be
+ * deducted from the pin number.
+ */
+struct gpio_name_num_table {
+	char bank;		/* bank name symbol */
+	u8 bank_size;		/* total number of pins in the bank */
+	char bank_offset;	/* offset of the first bank's pin */
+	unsigned int base;	/* index of the first bank's pin in the enum */
+};
 
-#define s5pc100_gpio_get(bank, pin) \
-			(S5P_GPIO_SET_PART(0) | \
-			S5PC100_SET_BANK(bank) | \
-			S5P_GPIO_SET_PIN(pin))
+#define GPIO_PER_BANK 8
+#define GPIO_ENTRY(name, base, top, offset) { name, top - base, offset, base }
+static const struct gpio_name_num_table s5pc100_gpio_table[] = {
+	GPIO_ENTRY('a', S5PC100_GPIO_A00, S5PC100_GPIO_B0, 0),
+	GPIO_ENTRY('b', S5PC100_GPIO_B0, S5PC100_GPIO_C0, 0),
+	GPIO_ENTRY('c', S5PC100_GPIO_C0, S5PC100_GPIO_D0, 0),
+	GPIO_ENTRY('d', S5PC100_GPIO_D0, S5PC100_GPIO_E00, 0),
+	GPIO_ENTRY('e', S5PC100_GPIO_E00, S5PC100_GPIO_F00, 0),
+	GPIO_ENTRY('f', S5PC100_GPIO_F00, S5PC100_GPIO_G00, 0),
+	GPIO_ENTRY('g', S5PC100_GPIO_G00, S5PC100_GPIO_I0, 0),
+	GPIO_ENTRY('i', S5PC100_GPIO_I0, S5PC100_GPIO_J00, 0),
+	GPIO_ENTRY('j', S5PC100_GPIO_J00, S5PC100_GPIO_K00, 0),
+	GPIO_ENTRY('k', S5PC100_GPIO_K00, S5PC100_GPIO_L00, 0),
+	GPIO_ENTRY('l', S5PC100_GPIO_L00, S5PC100_GPIO_H00, 0),
+	GPIO_ENTRY('h', S5PC100_GPIO_H00, S5PC100_GPIO_MAX_PORT, 0),
+	{ 0 }
+};
 
-#define s5pc110_gpio_get(bank, pin) \
-			(S5P_GPIO_SET_PART(0) | \
-			S5PC110_SET_BANK(bank) | \
-			S5P_GPIO_SET_PIN(pin))
+static const struct gpio_name_num_table s5pc110_gpio_table[] = {
+	GPIO_ENTRY('a', S5PC110_GPIO_A00, S5PC110_GPIO_B0, 0),
+	GPIO_ENTRY('b', S5PC110_GPIO_B0, S5PC110_GPIO_C00, 0),
+	GPIO_ENTRY('c', S5PC110_GPIO_C00, S5PC110_GPIO_D00, 0),
+	GPIO_ENTRY('d', S5PC110_GPIO_D00, S5PC110_GPIO_E00, 0),
+	GPIO_ENTRY('e', S5PC110_GPIO_E00, S5PC110_GPIO_F00, 0),
+	GPIO_ENTRY('f', S5PC110_GPIO_F00, S5PC110_GPIO_G00, 0),
+	GPIO_ENTRY('g', S5PC110_GPIO_G00, S5PC110_GPIO_I0, 0),
+	GPIO_ENTRY('i', S5PC110_GPIO_I0, S5PC110_GPIO_J00, 0),
+	GPIO_ENTRY('j', S5PC110_GPIO_J00, S5PC110_GPIO_MP010, 0),
+	GPIO_ENTRY('h', S5PC110_GPIO_H00, S5PC110_GPIO_MAX_PORT, 0),
+	{ 0 }
+};
 
-static inline unsigned int s5p_gpio_base(int nr)
-{
-	return samsung_get_base_gpio();
-}
+/* functions */
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_pull(int gpio, int mode);
+void gpio_set_drv(int gpio, int mode);
+int gpio_direction_output(unsigned gpio, int value);
+int gpio_set_value(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+void gpio_set_rate(int gpio, int mode);
+struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio);
+int s5p_gpio_get_pin(unsigned gpio);
+
+/* GPIO pins per bank  */
+#define GPIO_PER_BANK 8
 #endif
 
 /* Pin configurations */
-#define GPIO_INPUT	0x0
-#define GPIO_OUTPUT	0x1
-#define GPIO_IRQ	0xf
-#define GPIO_FUNC(x)	(x)
+#define S5P_GPIO_INPUT	0x0
+#define S5P_GPIO_OUTPUT	0x1
+#define S5P_GPIO_IRQ	0xf
+#define S5P_GPIO_FUNC(x)	(x)
 
 /* Pull mode */
-#define GPIO_PULL_NONE	0x0
-#define GPIO_PULL_DOWN	0x1
-#define GPIO_PULL_UP	0x2
+#define S5P_GPIO_PULL_NONE	0x0
+#define S5P_GPIO_PULL_DOWN	0x1
+#define S5P_GPIO_PULL_UP	0x2
 
 /* Drive Strength level */
-#define GPIO_DRV_1X	0x0
-#define GPIO_DRV_3X	0x1
-#define GPIO_DRV_2X	0x2
-#define GPIO_DRV_4X	0x3
-#define GPIO_DRV_FAST	0x0
-#define GPIO_DRV_SLOW	0x1
+#define S5P_GPIO_DRV_1X	0x0
+#define S5P_GPIO_DRV_3X	0x1
+#define S5P_GPIO_DRV_2X	0x2
+#define S5P_GPIO_DRV_4X	0x3
+#define S5P_GPIO_DRV_FAST	0x0
+#define S5P_GPIO_DRV_SLOW	0x1
 
 #endif
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
index d97190d..44cd455 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -14,11 +14,31 @@
 #define GPIO_FULLPORT(x)	((x) >> 3)
 #define GPIO_BIT(x)		((x) & 0x7)
 
+enum tegra_gpio_init {
+	TEGRA_GPIO_INIT_IN,
+	TEGRA_GPIO_INIT_OUT0,
+	TEGRA_GPIO_INIT_OUT1,
+};
+
+struct tegra_gpio_config {
+	u32 gpio:16;
+	u32 init:2;
+};
+
 /*
  * Tegra-specific GPIO API
  */
 
+/**
+ * Configure a list of GPIOs
+ *
+ * @param config	List of GPIO configurations
+ * @param len		Number of config items in list
+ */
+void gpio_config_table(const struct tegra_gpio_config *config, int len);
+
 void gpio_info(void);
 
 #define gpio_status()	gpio_info()
+
 #endif	/* TEGRA_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index 035159d..da47769 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -80,6 +80,11 @@ struct pmux_pingrp_config {
 #endif
 };
 
+#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
+/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
+void pinmux_set_tristate_input_clamping(void);
+#endif
+
 /* Set the mux function for a pin group */
 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
 
diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
index 310bbd7..84e7b55 100644
--- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h
+++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h
@@ -14,8 +14,6 @@
 /* for mmc_config definition */
 #include <mmc.h>
 
-#define MAX_HOSTS		4	/* Max number of 'hosts'/controllers */
-
 #ifndef __ASSEMBLY__
 struct tegra_mmc {
 	unsigned int	sysad;		/* _SYSTEM_ADDRESS_0 */
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index c1cb3ef..b86562a 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -231,6 +231,7 @@ enum pmux_drvgrp {
 };
 
 enum pmux_func {
+	PMUX_FUNC_DEFAULT,
 	PMUX_FUNC_BLINK,
 	PMUX_FUNC_CEC,
 	PMUX_FUNC_CLDVFS,
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index c49801c..1884935 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -247,6 +247,7 @@ enum pmux_drvgrp {
 };
 
 enum pmux_func {
+	PMUX_FUNC_DEFAULT,
 	PMUX_FUNC_BLINK,
 	PMUX_FUNC_CCLA,
 	PMUX_FUNC_CEC,
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 11c0104..f7bc97f 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -166,6 +166,7 @@ enum pmux_pingrp {
  * purely a convenience. The translation is done through a table search.
  */
 enum pmux_func {
+	PMUX_FUNC_DEFAULT,
 	PMUX_FUNC_AHB_CLK,
 	PMUX_FUNC_APB_CLK,
 	PMUX_FUNC_AUDIO_SYNC,
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index 6d83061..a42e009 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -306,6 +306,7 @@ enum pmux_drvgrp {
 };
 
 enum pmux_func {
+	PMUX_FUNC_DEFAULT,
 	PMUX_FUNC_BLINK,
 	PMUX_FUNC_CEC,
 	PMUX_FUNC_CLK_12M_OUT,
diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index dec11a1..cca920b 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -111,6 +111,11 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_DSE_40ohm	(6 << 3)
 #define PAD_CTL_DSE_34ohm	(7 << 3)
 
+#if defined CONFIG_MX6SL
+#define PAD_CTL_LVE		(1 << 1)
+#define PAD_CTL_LVE_BIT		(1 << 22)
+#endif
+
 #elif defined(CONFIG_VF610)
 
 #define PAD_MUX_MODE_SHIFT	20
diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h
new file mode 100644
index 0000000..2d94850
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/video.h
@@ -0,0 +1,24 @@
+/*
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __IMX_VIDEO_H_
+#define __IMX_VIDEO_H_
+
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+
+struct display_info_t {
+	int	bus;
+	int	addr;
+	int	pixfmt;
+	int	(*detect)(struct display_info_t const *dev);
+	void	(*enable)(struct display_info_t const *dev);
+	struct	fb_videomode mode;
+};
+
+#ifdef CONFIG_IMX_HDMI
+extern int detect_hdmi(struct display_info_t const *dev);
+#endif
+
+#endif