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authorR Sricharan <r.sricharan@ti.com>2013-03-04 20:04:45 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2013-03-28 09:10:58 +0100
commitde63ac278cbaaa387da3efaf0b21b819c2b0c496 (patch)
tree0fd5fac28bf5733062dee5a14881508569f4d709 /arch/arm/include/asm
parent96fdbec2f96c9e11758c8742409069eeef841722 (diff)
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ARM: mmu: Set domain permissions to client access
The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/system.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1918492..760345f 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -81,6 +81,20 @@ static inline void set_cr(unsigned int val)
isb();
}
+static inline unsigned int get_dacr(void)
+{
+ unsigned int val;
+ asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
+ return val;
+}
+
+static inline void set_dacr(unsigned int val)
+{
+ asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
+ : : "r" (val) : "cc");
+ isb();
+}
+
/* options available for data cache on each page */
enum dcache_option {
DCACHE_OFF = 0x12,