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| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 14:08:26 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-03-04 10:09:00 -0700 |
| commit | bc13472867beaf350b569a98c49a102476537e4f (patch) | |
| tree | e06e109d4f5c0b7ebb0ab2315cedb697ea328629 /arch/arm/include/asm | |
| parent | 439f57684e9fff3209f966365a18c328f858c623 (diff) | |
| download | u-boot-imx-bc13472867beaf350b569a98c49a102476537e4f.zip u-boot-imx-bc13472867beaf350b569a98c49a102476537e4f.tar.gz u-boot-imx-bc13472867beaf350b569a98c49a102476537e4f.tar.bz2 | |
ARM: tegra: pinmux: move some type definitions
On some future SoCs, some per-drive-group features became per-pin
features. Move all type definitions early in the header so they can
be enabled irrespective of the setting of TEGRA_PMX_SOC_HAS_DRVGRPS.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/pinmux.h | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h index cb61aa1..1562fa4 100644 --- a/arch/arm/include/asm/arch-tegra/pinmux.h +++ b/arch/arm/include/asm/arch-tegra/pinmux.h @@ -63,6 +63,35 @@ enum pmux_pin_rcv_sel { }; #endif +#ifdef TEGRA_PMX_GRPS_HAVE_LPMD +/* Defines a pin group cfg's low-power mode select */ +enum pmux_lpmd { + PMUX_LPMD_X8 = 0, + PMUX_LPMD_X4, + PMUX_LPMD_X2, + PMUX_LPMD_X, + PMUX_LPMD_NONE = -1, +}; +#endif + +#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT +/* Defines whether a pin group cfg's schmidt is enabled or not */ +enum pmux_schmt { + PMUX_SCHMT_DISABLE = 0, + PMUX_SCHMT_ENABLE = 1, + PMUX_SCHMT_NONE = -1, +}; +#endif + +#ifdef TEGRA_PMX_GRPS_HAVE_HSM +/* Defines whether a pin group cfg's high-speed mode is enabled or not */ +enum pmux_hsm { + PMUX_HSM_DISABLE = 0, + PMUX_HSM_ENABLE = 1, + PMUX_HSM_NONE = -1, +}; +#endif + /* * This defines the configuration for a pin, including the function assigned, * pull up/down settings and tristate settings. Having set up one of these @@ -142,35 +171,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, #define PMUX_DRVDN_MAX 127 #define PMUX_DRVDN_NONE -1 -#ifdef TEGRA_PMX_GRPS_HAVE_LPMD -/* Defines a pin group cfg's low-power mode select */ -enum pmux_lpmd { - PMUX_LPMD_X8 = 0, - PMUX_LPMD_X4, - PMUX_LPMD_X2, - PMUX_LPMD_X, - PMUX_LPMD_NONE = -1, -}; -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT -/* Defines whether a pin group cfg's schmidt is enabled or not */ -enum pmux_schmt { - PMUX_SCHMT_DISABLE = 0, - PMUX_SCHMT_ENABLE = 1, - PMUX_SCHMT_NONE = -1, -}; -#endif - -#ifdef TEGRA_PMX_GRPS_HAVE_HSM -/* Defines whether a pin group cfg's high-speed mode is enabled or not */ -enum pmux_hsm { - PMUX_HSM_DISABLE = 0, - PMUX_HSM_ENABLE = 1, - PMUX_HSM_NONE = -1, -}; -#endif - /* * This defines the configuration for a pin group's pad control config */ |