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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2012-05-22 00:03:25 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-07-07 14:07:24 +0200 |
| commit | 784ab7c545d25288a82216d18e2b0ca3beae470b (patch) | |
| tree | f2a631d64a5e279547eb0bbd64cf734a64dec28e /arch/arm/include/asm | |
| parent | 43037d76316db1a53be16a4c1ed97203257fa4ee (diff) | |
| download | u-boot-imx-784ab7c545d25288a82216d18e2b0ca3beae470b.zip u-boot-imx-784ab7c545d25288a82216d18e2b0ca3beae470b.tar.gz u-boot-imx-784ab7c545d25288a82216d18e2b0ca3beae470b.tar.bz2 | |
OMAP5: EMIF: Add support for DDR3 device
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/emif.h | 45 |
1 files changed, 44 insertions, 1 deletions
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5d2649e..c2ad877 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -471,6 +471,49 @@ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) +/*EMIF_READ_WRITE_LEVELING_CONTROL*/ +#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 +#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ +#define EMIF_REG_RDWRLVL_EN_SHIFT 31 +#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ +#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 +#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) + +/*Leveling Fields */ +#define DDR3_WR_LVL_INT 0x73 +#define DDR3_RD_LVL_INT 0x33 +#define DDR3_RD_LVL_GATE_INT 0x59 +#define RD_RW_LVL_INC_PRE 0x0 +#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) + +#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ + | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ + | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ + | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) + +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 +#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 + /* DMM */ #define DMM_BASE 0x4E000040 @@ -1104,5 +1147,5 @@ extern u32 *const T_den; extern u32 *const emif_sizes; #endif - +void config_data_eye_leveling_samples(u32 emif_base); #endif |