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authorStefano Babic <sbabic@denx.de>2014-04-29 17:41:19 +0200
committerStefano Babic <sbabic@denx.de>2014-04-29 17:41:19 +0200
commit3deb22a4844cbda1a05c60dd29d8926e4dddaa4e (patch)
tree767063f0d9e0acfd7445db47abf0d4ac94abdc1d /arch/arm/include/asm
parent3b31605aef069d183a9d0c1e3aa6f957503cd56b (diff)
parentc9aab0f9dd23fddcebf5984dc19e62b514e759a7 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/include/asm')
-rw-r--r--arch/arm/include/asm/arch-davinci/da850_lowlevel.h3
-rw-r--r--arch/arm/include/asm/arch-davinci/i2c_defs.h71
-rw-r--r--arch/arm/include/asm/arch-keystone/clock-k2hk.h109
-rw-r--r--arch/arm/include/asm/arch-keystone/clock.h17
-rw-r--r--arch/arm/include/asm/arch-keystone/clock_defs.h111
-rw-r--r--arch/arm/include/asm/arch-keystone/emac_defs.h240
-rw-r--r--arch/arm/include/asm/arch-keystone/emif_defs.h73
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware-k2hk.h150
-rw-r--r--arch/arm/include/asm/arch-keystone/hardware.h175
-rw-r--r--arch/arm/include/asm/arch-keystone/i2c_defs.h17
-rw-r--r--arch/arm/include/asm/arch-keystone/keystone_nav.h193
-rw-r--r--arch/arm/include/asm/arch-keystone/nand_defs.h23
-rw-r--r--arch/arm/include/asm/arch-keystone/psc_defs.h90
-rw-r--r--arch/arm/include/asm/arch-keystone/spl.h12
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h3
-rw-r--r--arch/arm/include/asm/arch-omap4/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h1
-rw-r--r--arch/arm/include/asm/arch-tegra/apb_misc.h (renamed from arch/arm/include/asm/arch-tegra20/apb_misc.h)2
-rw-r--r--arch/arm/include/asm/arch-tegra/board.h1
-rw-r--r--arch/arm/include/asm/arch-tegra/pinmux.h185
-rw-r--r--arch/arm/include/asm/arch-tegra/usb.h223
-rw-r--r--arch/arm/include/asm/arch-tegra114/pinmux.h836
-rw-r--r--arch/arm/include/asm/arch-tegra114/usb.h156
-rw-r--r--arch/arm/include/asm/arch-tegra124/pinmux.h866
-rw-r--r--arch/arm/include/asm/arch-tegra124/usb.h268
-rw-r--r--arch/arm/include/asm/arch-tegra20/pinmux.h372
-rw-r--r--arch/arm/include/asm/arch-tegra20/usb.h155
-rw-r--r--arch/arm/include/asm/arch-tegra30/pinmux.h963
-rw-r--r--arch/arm/include/asm/arch-tegra30/usb.h168
-rw-r--r--arch/arm/include/asm/omap_common.h2
30 files changed, 2672 insertions, 2814 deletions
diff --git a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
index 7f9c3f6..45a325c 100644
--- a/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
+++ b/arch/arm/include/asm/arch-davinci/da850_lowlevel.h
@@ -26,11 +26,8 @@ extern const int lpsc_size;
#define dv_maskbits(addr, val) \
writel((readl(addr) & val), addr)
-void da850_waitloop(unsigned long loopcnt);
-int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
void da850_lpc_transition(unsigned char pscnum, unsigned char module,
unsigned char domain, unsigned char state);
-int da850_ddr_setup(void);
void da850_psc_init(void);
void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
unsigned long value);
diff --git a/arch/arm/include/asm/arch-davinci/i2c_defs.h b/arch/arm/include/asm/arch-davinci/i2c_defs.h
index c388dc0..06da894 100644
--- a/arch/arm/include/asm/arch-davinci/i2c_defs.h
+++ b/arch/arm/include/asm/arch-davinci/i2c_defs.h
@@ -1,16 +1,13 @@
/*
- * (C) Copyright 2004
+ * (C) Copyright 2004-2014
* Texas Instruments, <www.ti.com>
*
* Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _DAVINCI_I2C_H_
-#define _DAVINCI_I2C_H_
-
-#define I2C_WRITE 0
-#define I2C_READ 1
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
#ifndef CONFIG_SOC_DA8XX
#define I2C_BASE 0x01c21000
@@ -18,66 +15,4 @@
#define I2C_BASE 0x01c22000
#endif
-#define I2C_OA (I2C_BASE + 0x00)
-#define I2C_IE (I2C_BASE + 0x04)
-#define I2C_STAT (I2C_BASE + 0x08)
-#define I2C_SCLL (I2C_BASE + 0x0c)
-#define I2C_SCLH (I2C_BASE + 0x10)
-#define I2C_CNT (I2C_BASE + 0x14)
-#define I2C_DRR (I2C_BASE + 0x18)
-#define I2C_SA (I2C_BASE + 0x1c)
-#define I2C_DXR (I2C_BASE + 0x20)
-#define I2C_CON (I2C_BASE + 0x24)
-#define I2C_IV (I2C_BASE + 0x28)
-#define I2C_PSC (I2C_BASE + 0x30)
-
-/* I2C masks */
-
-/* I2C Interrupt Enable Register (I2C_IE): */
-#define I2C_IE_SCD_IE (1 << 5) /* Stop condition detect interrupt enable */
-#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */
-#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */
-#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */
-#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */
-
-/* I2C Status Register (I2C_STAT): */
-
-#define I2C_STAT_BB (1 << 12) /* Bus busy */
-#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */
-#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
-#define I2C_STAT_AAS (1 << 9) /* Address as slave */
-#define I2C_STAT_SCD (1 << 5) /* Stop condition detect */
-#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
-#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */
-#define I2C_STAT_ARDY (1 << 2) /* Register access ready */
-#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */
-#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */
-
-
-/* I2C Interrupt Code Register (I2C_INTCODE): */
-
-#define I2C_INTCODE_MASK 7
-#define I2C_INTCODE_NONE 0
-#define I2C_INTCODE_AL 1 /* Arbitration lost */
-#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */
-#define I2C_INTCODE_ARDY 3 /* Register access ready */
-#define I2C_INTCODE_RRDY 4 /* Rcv data ready */
-#define I2C_INTCODE_XRDY 5 /* Xmit data ready */
-#define I2C_INTCODE_SCD 6 /* Stop condition detect */
-
-
-/* I2C Configuration Register (I2C_CON): */
-
-#define I2C_CON_EN (1 << 5) /* I2C module enable */
-#define I2C_CON_STB (1 << 4) /* Start byte mode (master mode only) */
-#define I2C_CON_MST (1 << 10) /* Master/slave mode */
-#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */
-#define I2C_CON_XA (1 << 8) /* Expand address */
-#define I2C_CON_STP (1 << 11) /* Stop condition (master mode only) */
-#define I2C_CON_STT (1 << 13) /* Start condition (master mode only) */
-#define I2C_CON_FREE (1 << 14) /* Free run on emulation */
-
-#define I2C_TIMEOUT 0xffff0000 /* Timeout mask for poll_i2c_irq() */
-
#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
new file mode 100644
index 0000000..6a69a8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h
@@ -0,0 +1,109 @@
+/*
+ * K2HK: Clock management APIs
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_K2HK_H
+#define __ASM_ARCH_CLOCK_K2HK_H
+
+#include <asm/arch/hardware.h>
+
+#ifndef __ASSEMBLY__
+
+enum ext_clk_e {
+ sys_clk,
+ alt_core_clk,
+ pa_clk,
+ tetris_clk,
+ ddr3a_clk,
+ ddr3b_clk,
+ mcm_clk,
+ pcie_clk,
+ sgmii_srio_clk,
+ xgmii_clk,
+ usb_clk,
+ rp1_clk,
+ ext_clk_count /* number of external clocks */
+};
+
+extern unsigned int external_clk[ext_clk_count];
+
+enum clk_e {
+ core_pll_clk,
+ pass_pll_clk,
+ tetris_pll_clk,
+ ddr3a_pll_clk,
+ ddr3b_pll_clk,
+ sys_clk0_clk,
+ sys_clk0_1_clk,
+ sys_clk0_2_clk,
+ sys_clk0_3_clk,
+ sys_clk0_4_clk,
+ sys_clk0_6_clk,
+ sys_clk0_8_clk,
+ sys_clk0_12_clk,
+ sys_clk0_24_clk,
+ sys_clk1_clk,
+ sys_clk1_3_clk,
+ sys_clk1_4_clk,
+ sys_clk1_6_clk,
+ sys_clk1_12_clk,
+ sys_clk2_clk,
+ sys_clk3_clk
+};
+
+#define K2HK_CLK1_6 sys_clk0_6_clk
+
+/* PLL identifiers */
+enum pll_type_e {
+ CORE_PLL,
+ PASS_PLL,
+ TETRIS_PLL,
+ DDR3A_PLL,
+ DDR3B_PLL,
+};
+#define MAIN_PLL CORE_PLL
+
+/* PLL configuration data */
+struct pll_init_data {
+ int pll;
+ int pll_m; /* PLL Multiplier */
+ int pll_d; /* PLL divider */
+ int pll_od; /* PLL output divider */
+};
+
+#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
+#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
+#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
+#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
+#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
+#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
+#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
+#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
+#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
+#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
+#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
+#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
+#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
+#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
+#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
+#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
+#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
+#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
+#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
+#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
+
+void init_plls(int num_pll, struct pll_init_data *config);
+void init_pll(const struct pll_init_data *data);
+unsigned long clk_get_rate(unsigned int clk);
+unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
+int clk_set_rate(unsigned int clk, unsigned long hz);
+
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
new file mode 100644
index 0000000..324501b
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock.h
@@ -0,0 +1,17 @@
+/*
+ * keystone2: common clock header file
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/clock-k2hk.h>
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h
new file mode 100644
index 0000000..b251aff
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/clock_defs.h
@@ -0,0 +1,111 @@
+/*
+ * keystone2: common pll clock definitions
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CLOCK_DEFS_H_
+#define _CLOCK_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+#define BIT(x) (1 << (x))
+
+/* PLL Control Registers */
+struct pllctl_regs {
+ u32 ctl; /* 00 */
+ u32 ocsel; /* 04 */
+ u32 secctl; /* 08 */
+ u32 resv0;
+ u32 mult; /* 10 */
+ u32 prediv; /* 14 */
+ u32 div1; /* 18 */
+ u32 div2; /* 1c */
+ u32 div3; /* 20 */
+ u32 oscdiv1; /* 24 */
+ u32 resv1; /* 28 */
+ u32 bpdiv; /* 2c */
+ u32 wakeup; /* 30 */
+ u32 resv2;
+ u32 cmd; /* 38 */
+ u32 stat; /* 3c */
+ u32 alnctl; /* 40 */
+ u32 dchange; /* 44 */
+ u32 cken; /* 48 */
+ u32 ckstat; /* 4c */
+ u32 systat; /* 50 */
+ u32 ckctl; /* 54 */
+ u32 resv3[2];
+ u32 div4; /* 60 */
+ u32 div5; /* 64 */
+ u32 div6; /* 68 */
+ u32 div7; /* 6c */
+ u32 div8; /* 70 */
+ u32 div9; /* 74 */
+ u32 div10; /* 78 */
+ u32 div11; /* 7c */
+ u32 div12; /* 80 */
+};
+
+static struct pllctl_regs *pllctl_regs[] = {
+ (struct pllctl_regs *)(CLOCK_BASE + 0x100)
+};
+
+#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg))
+#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg))
+#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg))
+
+#define pllctl_reg_rmw(pll, reg, mask, val) \
+ pllctl_reg_write(pll, reg, \
+ (pllctl_reg_read(pll, reg) & ~(mask)) | val)
+
+#define pllctl_reg_setbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, 0, mask)
+
+#define pllctl_reg_clrbits(pll, reg, mask) \
+ pllctl_reg_rmw(pll, reg, mask, 0)
+
+#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1)
+
+/* PLLCTL Bits */
+#define PLLCTL_BYPASS BIT(23)
+#define PLL_PLLRST BIT(14)
+#define PLLCTL_PAPLL BIT(13)
+#define PLLCTL_CLKMODE BIT(8)
+#define PLLCTL_PLLSELB BIT(7)
+#define PLLCTL_ENSAT BIT(6)
+#define PLLCTL_PLLENSRC BIT(5)
+#define PLLCTL_PLLDIS BIT(4)
+#define PLLCTL_PLLRST BIT(3)
+#define PLLCTL_PLLPWRDN BIT(1)
+#define PLLCTL_PLLEN BIT(0)
+#define PLLSTAT_GO BIT(0)
+
+#define MAIN_ENSAT_OFFSET 6
+
+#define PLLDIV_ENABLE BIT(15)
+
+#define PLL_DIV_MASK 0x3f
+#define PLL_MULT_MASK 0x1fff
+#define PLL_MULT_SHIFT 6
+#define PLLM_MULT_HI_MASK 0x7f
+#define PLLM_MULT_HI_SHIFT 12
+#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT)
+#define PLLM_MULT_LO_MASK 0x3f
+#define PLL_CLKOD_MASK 0xf
+#define PLL_CLKOD_SHIFT 19
+#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT)
+#define PLL_BWADJ_LO_MASK 0xff
+#define PLL_BWADJ_LO_SHIFT 24
+#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT)
+#define PLL_BWADJ_HI_MASK 0xf
+
+#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0)
+#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1)
+#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4)
+#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17)
+
+#endif /* _CLOCK_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h
new file mode 100644
index 0000000..0aa2f89
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/emac_defs.h
@@ -0,0 +1,240 @@
+/*
+ * emac definitions for keystone2 devices
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _EMAC_DEFS_H_
+#define _EMAC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define DEVICE_REG32_R(a) readl(a)
+#define DEVICE_REG32_W(a, v) writel(v, a)
+
+#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900)
+#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300)
+#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100)
+
+#define KEYSTONE2_EMAC_GIG_ENABLE
+
+#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110)
+
+#ifdef CONFIG_SOC_K2HK
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk))
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */
+#endif
+
+/* MII Status Register */
+#define MII_STATUS_REG 1
+#define MII_STATUS_LINK_MASK (0x4)
+
+/* Marvell 88E1111 PHY ID */
+#define PHY_MARVELL_88E1111 (0x01410cc0)
+
+#define MDIO_CONTROL_IDLE (0x80000000)
+#define MDIO_CONTROL_ENABLE (0x40000000)
+#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
+#define MDIO_CONTROL_FAULT (0x80000)
+#define MDIO_USERACCESS0_GO (0x80000000)
+#define MDIO_USERACCESS0_WRITE_READ (0x0)
+#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
+#define MDIO_USERACCESS0_ACK (0x20000000)
+
+#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
+#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
+#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
+#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
+#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
+
+#define EMAC_MIN_ETHERNET_PKT_SIZE 60
+
+struct mac_sl_cfg {
+ u_int32_t max_rx_len; /* Maximum receive packet length. */
+ u_int32_t ctl; /* Control bitfield */
+};
+
+/*
+ * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t
+ */
+#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24)
+#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23)
+#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22)
+#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18)
+#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17)
+#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16)
+#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15)
+#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11)
+#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10)
+#define GMACSL_ENABLE_GIG_MODE (1 << 7)
+#define GMACSL_TX_ENABLE_PACE (1 << 6)
+#define GMACSL_ENABLE (1 << 5)
+#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4)
+#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3)
+#define GMACSL_ENABLE_LOOPBACK (1 << 1)
+#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0)
+
+/*
+ * DEFINTITION: function return values
+ */
+#define GMACSL_RET_OK 0
+#define GMACSL_RET_INVALID_PORT -1
+#define GMACSL_RET_WARN_RESET_INCOMPLETE -2
+#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3
+#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4
+
+/* Register offsets */
+#define CPGMACSL_REG_ID 0x00
+#define CPGMACSL_REG_CTL 0x04
+#define CPGMACSL_REG_STATUS 0x08
+#define CPGMACSL_REG_RESET 0x0c
+#define CPGMACSL_REG_MAXLEN 0x10
+#define CPGMACSL_REG_BOFF 0x14
+#define CPGMACSL_REG_RX_PAUSE 0x18
+#define CPGMACSL_REG_TX_PAURSE 0x1c
+#define CPGMACSL_REG_EM_CTL 0x20
+#define CPGMACSL_REG_PRI 0x24
+
+/* Soft reset register values */
+#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0)
+#define CPGMAC_REG_RESET_VAL_RESET (1 << 0)
+
+/* Maxlen register values */
+#define CPGMAC_REG_MAXLEN_LEN 0x3fff
+
+/* Control bitfields */
+#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5)
+#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4)
+#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3)
+#define CPSW_CTL_P0_ENABLE (1 << 2)
+#define CPSW_CTL_VLAN_AWARE (1 << 1)
+#define CPSW_CTL_FIFO_LOOPBACK (1 << 0)
+
+#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */
+#define DEVICE_CPSW_BASE (0x02090800)
+#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */
+#define SWITCH_MAX_PKT_SIZE 9000
+
+/* Register offsets */
+#define CPSW_REG_CTL 0x004
+#define CPSW_REG_STAT_PORT_EN 0x00c
+#define CPSW_REG_MAXLEN 0x040
+#define CPSW_REG_ALE_CONTROL 0x608
+#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4)
+
+/* Register values */
+#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf
+#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000)
+#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010)
+#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3
+
+#define SGMII_REG_STATUS_LOCK BIT(4)
+#define SGMII_REG_STATUS_LINK BIT(0)
+#define SGMII_REG_STATUS_AUTONEG BIT(2)
+#define SGMII_REG_CONTROL_AUTONEG BIT(0)
+#define SGMII_REG_CONTROL_MASTER BIT(5)
+#define SGMII_REG_MR_ADV_ENABLE BIT(0)
+#define SGMII_REG_MR_ADV_LINK BIT(15)
+#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12)
+#define SGMII_REG_MR_ADV_GIG_MODE BIT(11)
+
+#define SGMII_LINK_MAC_MAC_AUTONEG 0
+#define SGMII_LINK_MAC_PHY 1
+#define SGMII_LINK_MAC_MAC_FORCED 2
+#define SGMII_LINK_MAC_FIBER 3
+#define SGMII_LINK_MAC_PHY_FORCED 4
+
+#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100
+#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \
+ KS2_PASS_BASE + 0x00090200, \
+ KS2_PASS_BASE + 0x00090400, \
+ KS2_PASS_BASE + 0x00090500}
+
+#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100))
+
+/*
+ * SGMII registers
+ */
+#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000)
+#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004)
+#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010)
+#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014)
+#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018)
+#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020)
+#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030)
+#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034)
+#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038)
+
+#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040)
+#define DEVICE_N_GMACSL_PORTS 4
+#define DEVICE_EMACSL_RESET_POLL_COUNT 100
+
+#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604)
+
+#ifdef CONFIG_SOC_K2HK
+#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606
+#endif
+
+#define hw_config_streaming_switch() \
+ DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \
+ DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI);
+
+/* EMAC MDIO Registers Structure */
+struct mdio_regs {
+ dv_reg version;
+ dv_reg control;
+ dv_reg alive;
+ dv_reg link;
+ dv_reg linkintraw;
+ dv_reg linkintmasked;
+ u_int8_t rsvd0[8];
+ dv_reg userintraw;
+ dv_reg userintmasked;
+ dv_reg userintmaskset;
+ dv_reg userintmaskclear;
+ u_int8_t rsvd1[80];
+ dv_reg useraccess0;
+ dv_reg userphysel0;
+ dv_reg useraccess1;
+ dv_reg userphysel1;
+};
+
+/* Ethernet MAC Registers Structure */
+struct emac_regs {
+ dv_reg idver;
+ dv_reg maccontrol;
+ dv_reg macstatus;
+ dv_reg soft_reset;
+ dv_reg rx_maxlen;
+ u32 rsvd0;
+ dv_reg rx_pause;
+ dv_reg tx_pause;
+ dv_reg emcontrol;
+ dv_reg pri_map;
+ u32 rsvd1[6];
+};
+
+#define SGMII_ACCESS(port, reg) \
+ *((volatile unsigned int *)(sgmiis[port] + reg))
+
+struct eth_priv_t {
+ char int_name[32];
+ int rx_flow;
+ int phy_addr;
+ int slave_port;
+ int sgmii_link_type;
+};
+
+extern struct eth_priv_t eth_priv_cfg[];
+
+int keystone2_emac_initialize(struct eth_priv_t *eth_priv);
+void sgmii_serdes_setup_156p25mhz(void);
+void sgmii_serdes_shutdown(void);
+
+#endif /* _EMAC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/emif_defs.h b/arch/arm/include/asm/arch-keystone/emif_defs.h
new file mode 100644
index 0000000..a3378aa
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/emif_defs.h
@@ -0,0 +1,73 @@
+/*
+ * emif definitions to re-use davinci emif driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _EMIF_DEFS_H_
+#define _EMIF_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+struct davinci_emif_regs {
+ uint32_t ercsr;
+ uint32_t awccr;
+ uint32_t sdbcr;
+ uint32_t sdrcr;
+ uint32_t abncr[4];
+ uint32_t sdtimr;
+ uint32_t ddrsr;
+ uint32_t ddrphycr;
+ uint32_t ddrphysr;
+ uint32_t totar;
+ uint32_t totactr;
+ uint32_t ddrphyid_rev;
+ uint32_t sdsretr;
+ uint32_t eirr;
+ uint32_t eimr;
+ uint32_t eimsr;
+ uint32_t eimcr;
+ uint32_t ioctrlr;
+ uint32_t iostatr;
+ uint32_t rsvd0;
+ uint32_t one_nand_cr;
+ uint32_t nandfcr;
+ uint32_t nandfsr;
+ uint32_t rsvd1[2];
+ uint32_t nandfecc[4];
+ uint32_t rsvd2[15];
+ uint32_t nand4biteccload;
+ uint32_t nand4bitecc[4];
+ uint32_t nanderradd1;
+ uint32_t nanderradd2;
+ uint32_t nanderrval1;
+ uint32_t nanderrval2;
+};
+
+#define davinci_emif_regs \
+ ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
+
+#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
+#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
+#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
+#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
+#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
+
+/* Chip Select setup */
+#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
+#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
+#define DAVINCI_ABCR_WSETUP(n) ((n) << 26)
+#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20)
+#define DAVINCI_ABCR_WHOLD(n) ((n) << 17)
+#define DAVINCI_ABCR_RSETUP(n) ((n) << 13)
+#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7)
+#define DAVINCI_ABCR_RHOLD(n) ((n) << 4)
+#define DAVINCI_ABCR_TA(n) ((n) << 2)
+#define DAVINCI_ABCR_ASIZE_16BIT 1
+#define DAVINCI_ABCR_ASIZE_8BIT 0
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
new file mode 100644
index 0000000..50ff13a
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -0,0 +1,150 @@
+/*
+ * K2HK: SoC definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_K2HK_H
+#define __ASM_ARCH_HARDWARE_K2HK_H
+
+#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE
+#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000
+#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000
+#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000
+#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000
+
+#define K2HK_PLL_CNTRL_BASE 0x02310000
+#define CLOCK_BASE K2HK_PLL_CNTRL_BASE
+#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8)
+#define KS2_RSTCTRL_KEY 0x5a69
+#define KS2_RSTCTRL_MASK 0xffff0000
+#define KS2_RSTCTRL_SWRST 0xfffe0000
+
+#define K2HK_PSC_BASE 0x02350000
+#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000
+#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
+#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
+
+#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
+
+#define ARM_PLL_EN BIT(13)
+
+#define K2HK_SPI0_BASE 0x21000400
+#define K2HK_SPI1_BASE 0x21000600
+#define K2HK_SPI2_BASE 0x21000800
+#define K2HK_SPI_BASE K2HK_SPI0_BASE
+
+/* Chip configuration unlock codes and registers */
+#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
+#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
+#define KEYSTONE_KICK0_MAGIC 0x83e70b13
+#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0
+
+/* PA SS Registers */
+#define KS2_PASS_BASE 0x02000000
+
+/* PLL control registers */
+#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
+#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
+#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
+#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
+#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
+#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
+#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
+#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
+#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
+#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
+
+/* Power and Sleep Controller (PSC) Domains */
+#define K2HK_LPSC_MOD 0
+#define K2HK_LPSC_DUMMY1 1
+#define K2HK_LPSC_USB 2
+#define K2HK_LPSC_EMIF25_SPI 3
+#define K2HK_LPSC_TSIP 4
+#define K2HK_LPSC_DEBUGSS_TRC 5
+#define K2HK_LPSC_TETB_TRC 6
+#define K2HK_LPSC_PKTPROC 7
+#define KS2_LPSC_PA K2HK_LPSC_PKTPROC
+#define K2HK_LPSC_SGMII 8
+#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII
+#define K2HK_LPSC_CRYPTO 9
+#define K2HK_LPSC_PCIE 10
+#define K2HK_LPSC_SRIO 11
+#define K2HK_LPSC_VUSR0 12
+#define K2HK_LPSC_CHIP_SRSS 13
+#define K2HK_LPSC_MSMC 14
+#define K2HK_LPSC_GEM_0 15
+#define K2HK_LPSC_GEM_1 16
+#define K2HK_LPSC_GEM_2 17
+#define K2HK_LPSC_GEM_3 18
+#define K2HK_LPSC_GEM_4 19
+#define K2HK_LPSC_GEM_5 20
+#define K2HK_LPSC_GEM_6 21
+#define K2HK_LPSC_GEM_7 22
+#define K2HK_LPSC_EMIF4F_DDR3A 23
+#define K2HK_LPSC_EMIF4F_DDR3B 24
+#define K2HK_LPSC_TAC 25
+#define K2HK_LPSC_RAC 26
+#define K2HK_LPSC_RAC_1 27
+#define K2HK_LPSC_FFTC_A 28
+#define K2HK_LPSC_FFTC_B 29
+#define K2HK_LPSC_FFTC_C 30
+#define K2HK_LPSC_FFTC_D 31
+#define K2HK_LPSC_FFTC_E 32
+#define K2HK_LPSC_FFTC_F 33
+#define K2HK_LPSC_AI2 34
+#define K2HK_LPSC_TCP3D_0 35
+#define K2HK_LPSC_TCP3D_1 36
+#define K2HK_LPSC_TCP3D_2 37
+#define K2HK_LPSC_TCP3D_3 38
+#define K2HK_LPSC_VCP2X4_A 39
+#define K2HK_LPSC_CP2X4_B 40
+#define K2HK_LPSC_VCP2X4_C 41
+#define K2HK_LPSC_VCP2X4_D 42
+#define K2HK_LPSC_VCP2X4_E 43
+#define K2HK_LPSC_VCP2X4_F 44
+#define K2HK_LPSC_VCP2X4_G 45
+#define K2HK_LPSC_VCP2X4_H 46
+#define K2HK_LPSC_BCP 47
+#define K2HK_LPSC_DXB 48
+#define K2HK_LPSC_VUSR1 49
+#define K2HK_LPSC_XGE 50
+#define K2HK_LPSC_ARM_SREFLEX 51
+#define K2HK_LPSC_TETRIS 52
+
+#define K2HK_UART0_BASE 0x02530c00
+
+/* DDR3A definitions */
+#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
+#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
+#define K2HK_DDR3A_DDRPHYC 0x02329000
+/* DDR3B definitions */
+#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000
+#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000
+#define K2HK_DDR3B_DDRPHYC 0x02328000
+
+/* Queue manager */
+#define DEVICE_QM_MANAGER_BASE 0x02a02000
+#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000
+#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000
+#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
+#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000
+#define DEVICE_QM_NUM_LINKRAMS 2
+#define DEVICE_QM_NUM_MEMREGIONS 20
+
+#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000
+#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
+#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
+#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
+
+#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24
+#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32
+#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9
+
+/* MSMC control */
+#define K2HK_MSMC_CTRL_BASE 0x0bc00000
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h
new file mode 100644
index 0000000..a305a0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/hardware.h
@@ -0,0 +1,175 @@
+/*
+ * Keystone2: Common SoC definitions, structures etc.
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/sizes.h>
+#include <asm/io.h>
+
+#define REG(addr) (*(volatile unsigned int *)(addr))
+#define REG_P(addr) ((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int dv_reg;
+typedef volatile unsigned int *dv_reg_p;
+
+#define ASYNC_EMIF_NUM_CS 4
+#define ASYNC_EMIF_MODE_NOR 0
+#define ASYNC_EMIF_MODE_NAND 1
+#define ASYNC_EMIF_MODE_ONENAND 2
+#define ASYNC_EMIF_PRESERVE -1
+
+struct async_emif_config {
+ unsigned mode;
+ unsigned select_strobe;
+ unsigned extend_wait;
+ unsigned wr_setup;
+ unsigned wr_strobe;
+ unsigned wr_hold;
+ unsigned rd_setup;
+ unsigned rd_strobe;
+ unsigned rd_hold;
+ unsigned turn_around;
+ enum {
+ ASYNC_EMIF_8 = 0,
+ ASYNC_EMIF_16 = 1,
+ ASYNC_EMIF_32 = 2,
+ } width;
+};
+
+void init_async_emif(int num_cs, struct async_emif_config *config);
+
+struct ddr3_phy_config {
+ unsigned int pllcr;
+ unsigned int pgcr1_mask;
+ unsigned int pgcr1_val;
+ unsigned int ptr0;
+ unsigned int ptr1;
+ unsigned int ptr2;
+ unsigned int ptr3;
+ unsigned int ptr4;
+ unsigned int dcr_mask;
+ unsigned int dcr_val;
+ unsigned int dtpr0;
+ unsigned int dtpr1;
+ unsigned int dtpr2;
+ unsigned int mr0;
+ unsigned int mr1;
+ unsigned int mr2;
+ unsigned int dtcr;
+ unsigned int pgcr2;
+ unsigned int zq0cr1;
+ unsigned int zq1cr1;
+ unsigned int zq2cr1;
+ unsigned int pir_v1;
+ unsigned int pir_v2;
+};
+
+struct ddr3_emif_config {
+ unsigned int sdcfg;
+ unsigned int sdtim1;
+ unsigned int sdtim2;
+ unsigned int sdtim3;
+ unsigned int sdtim4;
+ unsigned int zqcfg;
+ unsigned int sdrfc;
+};
+
+#endif
+
+#define BIT(x) (1 << (x))
+
+#define KS2_DDRPHY_PIR_OFFSET 0x04
+#define KS2_DDRPHY_PGCR0_OFFSET 0x08
+#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
+#define KS2_DDRPHY_PGSR0_OFFSET 0x10
+#define KS2_DDRPHY_PGSR1_OFFSET 0x14
+#define KS2_DDRPHY_PLLCR_OFFSET 0x18
+#define KS2_DDRPHY_PTR0_OFFSET 0x1C
+#define KS2_DDRPHY_PTR1_OFFSET 0x20
+#define KS2_DDRPHY_PTR2_OFFSET 0x24
+#define KS2_DDRPHY_PTR3_OFFSET 0x28
+#define KS2_DDRPHY_PTR4_OFFSET 0x2C
+#define KS2_DDRPHY_DCR_OFFSET 0x44
+
+#define KS2_DDRPHY_DTPR0_OFFSET 0x48
+#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
+#define KS2_DDRPHY_DTPR2_OFFSET 0x50
+
+#define KS2_DDRPHY_MR0_OFFSET 0x54
+#define KS2_DDRPHY_MR1_OFFSET 0x58
+#define KS2_DDRPHY_MR2_OFFSET 0x5C
+#define KS2_DDRPHY_DTCR_OFFSET 0x68
+#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
+
+#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
+#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
+#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
+#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
+
+#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
+
+#define IODDRM_MASK 0x00000180
+#define ZCKSEL_MASK 0x01800000
+#define CL_MASK 0x00000072
+#define WR_MASK 0x00000E00
+#define BL_MASK 0x00000003
+#define RRMODE_MASK 0x00040000
+#define UDIMM_MASK 0x20000000
+#define BYTEMASK_MASK 0x0003FC00
+#define MPRDQ_MASK 0x00000080
+#define PDQ_MASK 0x00000070
+#define NOSRA_MASK 0x08000000
+#define ECC_MASK 0x00000001
+
+#define KS2_DDR3_MIDR_OFFSET 0x00
+#define KS2_DDR3_STATUS_OFFSET 0x04
+#define KS2_DDR3_SDCFG_OFFSET 0x08
+#define KS2_DDR3_SDRFC_OFFSET 0x10
+#define KS2_DDR3_SDTIM1_OFFSET 0x18
+#define KS2_DDR3_SDTIM2_OFFSET 0x1C
+#define KS2_DDR3_SDTIM3_OFFSET 0x20
+#define KS2_DDR3_SDTIM4_OFFSET 0x28
+#define KS2_DDR3_PMCTL_OFFSET 0x38
+#define KS2_DDR3_ZQCFG_OFFSET 0xC8
+
+#ifdef CONFIG_SOC_K2HK
+#include <asm/arch/hardware-k2hk.h>
+#endif
+
+#ifndef __ASSEMBLY__
+static inline int cpu_is_k2hk(void)
+{
+ unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int part_no = (jtag_id >> 12) & 0xffff;
+
+ return (part_no == 0xb981) ? 1 : 0;
+}
+
+static inline int cpu_revision(void)
+{
+ unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
+ unsigned int rev = (jtag_id >> 28) & 0xf;
+
+ return rev;
+}
+
+void share_all_segments(int priv_id);
+int cpu_to_bus(u32 *ptr, u32 length);
+void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
+void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
+void init_ddr3(void);
+void sdelay(unsigned long);
+
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/include/asm/arch-keystone/i2c_defs.h
new file mode 100644
index 0000000..d425652
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/i2c_defs.h
@@ -0,0 +1,17 @@
+/*
+ * keystone: i2c driver definitions
+ *
+ * (C) Copyright 2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
+
+#define I2C0_BASE 0x02530000
+#define I2C1_BASE 0x02530400
+#define I2C2_BASE 0x02530800
+#define I2C_BASE I2C0_BASE
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/keystone_nav.h b/arch/arm/include/asm/arch-keystone/keystone_nav.h
new file mode 100644
index 0000000..ab81eaf
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/keystone_nav.h
@@ -0,0 +1,193 @@
+/*
+ * Multicore Navigator definitions
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _KEYSTONE_NAV_H_
+#define _KEYSTONE_NAV_H_
+
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+enum soc_type_t {
+ k2hk
+};
+
+#define QM_OK 0
+#define QM_ERR -1
+#define QM_DESC_TYPE_HOST 0
+#define QM_DESC_PSINFO_IN_DESCR 0
+#define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \
+ (QM_DESC_PSINFO_IN_DESCR << 22)
+
+/* Packet Info */
+#define QM_DESC_PINFO_EPIB 1
+#define QM_DESC_PINFO_RETURN_OWN 1
+#define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \
+ (QM_DESC_PINFO_RETURN_OWN << 15)
+
+struct qm_cfg_reg {
+ u32 revision;
+ u32 __pad1;
+ u32 divert;
+ u32 link_ram_base0;
+ u32 link_ram_size0;
+ u32 link_ram_base1;
+ u32 link_ram_size1;
+ u32 link_ram_base2;
+ u32 starvation[0];
+};
+
+struct descr_mem_setup_reg {
+ u32 base_addr;
+ u32 start_idx;
+ u32 desc_reg_size;
+ u32 _res0;
+};
+
+struct qm_reg_queue {
+ u32 entry_count;
+ u32 byte_count;
+ u32 packet_size;
+ u32 ptr_size_thresh;
+};
+
+struct qm_config {
+ /* QM module addresses */
+ u32 stat_cfg; /* status and config */
+ struct qm_reg_queue *queue; /* management region */
+ u32 mngr_vbusm; /* management region (VBUSM) */
+ u32 i_lram; /* internal linking RAM */
+ struct qm_reg_queue *proxy;
+ u32 status_ram;
+ struct qm_cfg_reg *mngr_cfg;
+ /* Queue manager config region */
+ u32 intd_cfg; /* QMSS INTD config region */
+ struct descr_mem_setup_reg *desc_mem;
+ /* descritor memory setup region*/
+ u32 region_num;
+ u32 pdsp_cmd; /* PDSP1 command interface */
+ u32 pdsp_ctl; /* PDSP1 control registers */
+ u32 pdsp_iram;
+ /* QM configuration parameters */
+
+ u32 qpool_num; /* */
+};
+
+struct qm_host_desc {
+ u32 desc_info;
+ u32 tag_info;
+ u32 packet_info;
+ u32 buff_len;
+ u32 buff_ptr;
+ u32 next_bdptr;
+ u32 orig_buff_len;
+ u32 orig_buff_ptr;
+ u32 timestamp;
+ u32 swinfo[3];
+ u32 ps_data[20];
+};
+
+#define HDESC_NUM 256
+
+int qm_init(void);
+void qm_close(void);
+void qm_push(struct qm_host_desc *hd, u32 qnum);
+struct qm_host_desc *qm_pop(u32 qnum);
+
+void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
+ void *buff_ptr, u32 buff_len);
+
+struct qm_host_desc *qm_pop_from_free_pool(void);
+void queue_close(u32 qnum);
+
+/*
+ * DMA API
+ */
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
+ psloc, sopoff, qmgr, qnum) \
+ (((einfo & 1) << 30) | \
+ ((psinfo & 1) << 29) | \
+ ((rxerr & 1) << 28) | \
+ ((desc & 3) << 26) | \
+ ((psloc & 1) << 25) | \
+ ((sopoff & 0x1ff) << 16) | \
+ ((qmgr & 3) << 12) | \
+ ((qnum & 0xfff) << 0))
+
+#define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
+ (((fd0qm & 3) << 28) | \
+ ((fd0qnum & 0xfff) << 16) | \
+ ((fd1qm & 3) << 12) | \
+ ((fd1qnum & 0xfff) << 0))
+
+#define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
+#define CPDMA_CHAN_A_TDOWN (1 << 30)
+#define TDOWN_TIMEOUT_COUNT 100
+
+struct global_ctl_regs {
+ u32 revision;
+ u32 perf_control;
+ u32 emulation_control;
+ u32 priority_control;
+ u32 qm_base_addr[4];
+};
+
+struct tx_chan_regs {
+ u32 cfg_a;
+ u32 cfg_b;
+ u32 res[6];
+};
+
+struct rx_chan_regs {
+ u32 cfg_a;
+ u32 res[7];
+};
+
+struct rx_flow_regs {
+ u32 control;
+ u32 tags;
+ u32 tag_sel;
+ u32 fdq_sel[2];
+ u32 thresh[3];
+};
+
+struct pktdma_cfg {
+ struct global_ctl_regs *global;
+ struct tx_chan_regs *tx_ch;
+ u32 tx_ch_num;
+ struct rx_chan_regs *rx_ch;
+ u32 rx_ch_num;
+ u32 *tx_sched;
+ struct rx_flow_regs *rx_flows;
+ u32 rx_flow_num;
+
+ u32 rx_free_q;
+ u32 rx_rcv_q;
+ u32 tx_snd_q;
+
+ u32 rx_flow; /* flow that is used for RX */
+};
+
+/*
+ * packet dma user allocates memory for rx buffers
+ * and describe it in the following structure
+ */
+struct rx_buff_desc {
+ u8 *buff_ptr;
+ u32 num_buffs;
+ u32 buff_len;
+ u32 rx_flow;
+};
+
+int netcp_close(void);
+int netcp_init(struct rx_buff_desc *rx_buffers);
+int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
+void *netcp_recv(u32 **pkt, int *num_bytes);
+void netcp_release_rxhd(void *hd);
+
+#endif /* _KEYSTONE_NAV_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/nand_defs.h b/arch/arm/include/asm/arch-keystone/nand_defs.h
new file mode 100644
index 0000000..58417db
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/nand_defs.h
@@ -0,0 +1,23 @@
+/*
+ * nand driver definitions to re-use davinci nand driver on Keystone2
+ *
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _NAND_DEFS_H_
+#define _NAND_DEFS_H_
+
+#include <asm/arch/hardware.h>
+#include <linux/mtd/nand.h>
+
+#define MASK_CLE 0x4000
+#define MASK_ALE 0x2000
+
+#define NAND_READ_START 0x00
+#define NAND_READ_END 0x30
+#define NAND_STATUS 0x70
+
+#endif
diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/include/asm/arch-keystone/psc_defs.h
new file mode 100644
index 0000000..70d22cf
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/psc_defs.h
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _PSC_DEFS_H_
+#define _PSC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+/*
+ * FILE PURPOSE: Local Power Sleep Controller definitions
+ *
+ * FILE NAME: psc_defs.h
+ *
+ * DESCRIPTION: Provides local definitions for the power saver controller
+ *
+ */
+
+/* Register offsets */
+#define PSC_REG_PTCMD 0x120
+#define PSC_REG_PSTAT 0x128
+#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x)))
+#define PSC_REG_PDCTL(x) (0x300 + (4 * (x)))
+#define PSC_REG_MDCFG(x) (0x600 + (4 * (x)))
+#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x)))
+#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x)))
+
+#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \
+ (u32)1)) << ((u32)y)))
+
+#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y)
+#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \
+ ((((u32)f) << (y)) & BOOTBITMASK(x, y))
+
+/* PDCTL */
+#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0)
+#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12)
+
+/* PDSTAT */
+#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0)
+
+/* MDCFG */
+#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16)
+#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14)
+
+/* MDCTL */
+#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0)
+#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8)
+#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \
+ 12, 12)
+
+/* MDSTAT */
+#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0)
+#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8)
+#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9)
+
+/* PDCTL states */
+#define PSC_REG_VAL_PDCTL_NEXT_ON 1
+#define PSC_REG_VAL_PDCTL_NEXT_OFF 0
+
+#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0
+
+/* MDCTL states */
+#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0
+#define PSC_REG_VAL_MDCTL_NEXT_OFF 2
+#define PSC_REG_VAL_MDCTL_NEXT_ON 3
+
+/* MDSTAT states */
+#define PSC_REG_VAL_MDSTAT_STATE_ON 3
+#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24
+#define PSC_REG_VAL_MDSTAT_STATE_OFF 2
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21
+#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22
+
+/*
+ * Timeout limit on checking PTSTAT. This is the number of times the
+ * wait function will be called before giving up.
+ */
+#define PSC_PTSTAT_TIMEOUT_LIMIT 100
+
+u32 psc_get_domain_num(u32 mod_num);
+int psc_enable_module(u32 mod_num);
+int psc_disable_module(u32 mod_num);
+int psc_disable_domain(u32 domain_num);
+
+#endif /* _PSC_DEFS_H_ */
diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h
new file mode 100644
index 0000000..7012ea7
--- /dev/null
+++ b/arch/arm/include/asm/arch-keystone/spl.h
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2012-2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_SPL_H_
+#define _ASM_SPL_H_
+
+#define BOOT_DEVICE_SPI 2
+
+#endif
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 44fa66f..5866bf2 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -8,6 +8,7 @@
#ifndef _SYS_PROTO_H_
#define _SYS_PROTO_H_
#include <linux/mtd/omap_gpmc.h>
+#include <asm/omap_common.h>
typedef struct {
u32 mtype;
@@ -62,13 +63,13 @@ void secureworld_exit(void);
void try_unlock_memory(void);
u32 get_boot_type(void);
void invalidate_dcache(u32);
-void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void make_cs1_contiguous(void);
void omap_nand_switch_ecc(uint32_t, uint32_t);
void power_init_r(void);
void dieid_num_r(void);
+void get_dieid(u32 *id);
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
u32 warm_reset(void);
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index b338a15..80172f3 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -31,7 +31,6 @@ void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void set_pl310_ctrl_reg(u32 val);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 9e007c8..bf12c73 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -32,7 +32,6 @@ void watchdog_init(void);
u32 get_device_type(void);
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
void set_muxconf_regs_essential(void);
-void sr32(void *, u32, u32, u32);
u32 wait_on_value(u32, u32, void *, u32);
void sdelay(unsigned long);
void setup_clocks_for_console(void);
diff --git a/arch/arm/include/asm/arch-tegra20/apb_misc.h b/arch/arm/include/asm/arch-tegra/apb_misc.h
index f314f5a..a5bc092 100644
--- a/arch/arm/include/asm/arch-tegra20/apb_misc.h
+++ b/arch/arm/include/asm/arch-tegra/apb_misc.h
@@ -11,6 +11,8 @@
struct apb_misc_pp_ctlr {
u32 reserved0[2];
u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */
+ u32 reserved1[6]; /* 0x0c .. 0x20 */
+ u32 cfg_ctl; /* 0x24 */
};
/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */
diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h
index 0e69864..ff77364 100644
--- a/arch/arm/include/asm/arch-tegra/board.h
+++ b/arch/arm/include/asm/arch-tegra/board.h
@@ -24,6 +24,7 @@ void gpio_early_init(void); /* overrideable GPIO config */
* an empty stub function will be called.
*/
+void pinmux_init(void); /* overrideable general pinmux setup */
void pin_mux_usb(void); /* overrideable USB pinmux setup */
void pin_mux_spi(void); /* overrideable SPI pinmux setup */
void pin_mux_nand(void); /* overrideable NAND pinmux setup */
diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
new file mode 100644
index 0000000..035159d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2010-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _TEGRA_PINMUX_H_
+#define _TEGRA_PINMUX_H_
+
+#include <asm/arch/tegra.h>
+
+/* The pullup/pulldown state of a pin group */
+enum pmux_pull {
+ PMUX_PULL_NORMAL = 0,
+ PMUX_PULL_DOWN,
+ PMUX_PULL_UP,
+};
+
+/* Defines whether a pin group is tristated or in normal operation */
+enum pmux_tristate {
+ PMUX_TRI_NORMAL = 0,
+ PMUX_TRI_TRISTATE = 1,
+};
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+enum pmux_pin_io {
+ PMUX_PIN_OUTPUT = 0,
+ PMUX_PIN_INPUT = 1,
+ PMUX_PIN_NONE,
+};
+
+enum pmux_pin_lock {
+ PMUX_PIN_LOCK_DEFAULT = 0,
+ PMUX_PIN_LOCK_DISABLE,
+ PMUX_PIN_LOCK_ENABLE,
+};
+
+enum pmux_pin_od {
+ PMUX_PIN_OD_DEFAULT = 0,
+ PMUX_PIN_OD_DISABLE,
+ PMUX_PIN_OD_ENABLE,
+};
+
+enum pmux_pin_ioreset {
+ PMUX_PIN_IO_RESET_DEFAULT = 0,
+ PMUX_PIN_IO_RESET_DISABLE,
+ PMUX_PIN_IO_RESET_ENABLE,
+};
+
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+enum pmux_pin_rcv_sel {
+ PMUX_PIN_RCV_SEL_DEFAULT = 0,
+ PMUX_PIN_RCV_SEL_NORMAL,
+ PMUX_PIN_RCV_SEL_HIGH,
+};
+#endif /* TEGRA_PMX_HAS_RCV_SEL */
+#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
+
+/*
+ * This defines the configuration for a pin, including the function assigned,
+ * pull up/down settings and tristate settings. Having set up one of these
+ * you can call pinmux_config_pingroup() to configure a pin in one step. Also
+ * available is pinmux_config_table() to configure a list of pins.
+ */
+struct pmux_pingrp_config {
+ u32 pingrp:16; /* pin group PMUX_PINGRP_... */
+ u32 func:8; /* function to assign PMUX_FUNC_... */
+ u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/
+ u32 tristate:2; /* tristate or normal PMUX_TRI_... */
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+ u32 io:2; /* input or output PMUX_PIN_... */
+ u32 lock:2; /* lock enable/disable PMUX_PIN... */
+ u32 od:2; /* open-drain or push-pull driver */
+ u32 ioreset:2; /* input/output reset PMUX_PIN... */
+#ifdef TEGRA_PMX_HAS_RCV_SEL
+ u32 rcv_sel:2; /* select between High and Normal */
+ /* VIL/VIH receivers */
+#endif
+#endif
+};
+
+/* Set the mux function for a pin group */
+void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
+
+/* Set the pull up/down feature for a pin group */
+void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
+
+/* Set a pin group to tristate */
+void pinmux_tristate_enable(enum pmux_pingrp pin);
+
+/* Set a pin group to normal (non tristate) */
+void pinmux_tristate_disable(enum pmux_pingrp pin);
+
+#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+/* Set a pin group as input or output */
+void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
+#endif
+
+/**
+ * Configure a list of pin groups
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
+ int len);
+
+#ifdef TEGRA_PMX_HAS_DRVGRPS
+
+#define PMUX_SLWF_MIN 0
+#define PMUX_SLWF_MAX 3
+#define PMUX_SLWF_NONE -1
+
+#define PMUX_SLWR_MIN 0
+#define PMUX_SLWR_MAX 3
+#define PMUX_SLWR_NONE -1
+
+#define PMUX_DRVUP_MIN 0
+#define PMUX_DRVUP_MAX 127
+#define PMUX_DRVUP_NONE -1
+
+#define PMUX_DRVDN_MIN 0
+#define PMUX_DRVDN_MAX 127
+#define PMUX_DRVDN_NONE -1
+
+/* Defines a pin group cfg's low-power mode select */
+enum pmux_lpmd {
+ PMUX_LPMD_X8 = 0,
+ PMUX_LPMD_X4,
+ PMUX_LPMD_X2,
+ PMUX_LPMD_X,
+ PMUX_LPMD_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's schmidt is enabled or not */
+enum pmux_schmt {
+ PMUX_SCHMT_DISABLE = 0,
+ PMUX_SCHMT_ENABLE = 1,
+ PMUX_SCHMT_NONE = -1,
+};
+
+/* Defines whether a pin group cfg's high-speed mode is enabled or not */
+enum pmux_hsm {
+ PMUX_HSM_DISABLE = 0,
+ PMUX_HSM_ENABLE = 1,
+ PMUX_HSM_NONE = -1,
+};
+
+/*
+ * This defines the configuration for a pin group's pad control config
+ */
+struct pmux_drvgrp_config {
+ u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */
+ u32 slwf:3; /* falling edge slew */
+ u32 slwr:3; /* rising edge slew */
+ u32 drvup:8; /* pull-up drive strength */
+ u32 drvdn:8; /* pull-down drive strength */
+ u32 lpmd:3; /* low-power mode selection */
+ u32 schmt:2; /* schmidt enable */
+ u32 hsm:2; /* high-speed mode enable */
+};
+
+/**
+ * Set the GP pad configs
+ *
+ * @param config List of config items
+ * @param len Number of config items in list
+ */
+void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
+ int len);
+
+#endif /* TEGRA_PMX_HAS_DRVGRPS */
+
+struct pmux_pingrp_desc {
+ u8 funcs[4];
+#if defined(CONFIG_TEGRA20)
+ u8 ctl_id;
+ u8 pull_id;
+#endif /* CONFIG_TEGRA20 */
+};
+
+extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
+
+#endif /* _TEGRA_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra/usb.h b/arch/arm/include/asm/arch-tegra/usb.h
index a1efd07..ceb7bcd 100644
--- a/arch/arm/include/asm/arch-tegra/usb.h
+++ b/arch/arm/include/asm/arch-tegra/usb.h
@@ -8,6 +8,189 @@
#ifndef _TEGRA_USB_H_
#define _TEGRA_USB_H_
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+ /* 0x000 */
+ uint id;
+ uint reserved0;
+ uint host;
+ uint device;
+
+ /* 0x010 */
+ uint txbuf;
+ uint rxbuf;
+ uint reserved1[2];
+
+ /* 0x020 */
+ uint reserved2[56];
+
+ /* 0x100 */
+ u16 cap_length;
+ u16 hci_version;
+ uint hcs_params;
+ uint hcc_params;
+ uint reserved3[5];
+
+ /* 0x120 */
+ uint dci_version;
+ uint dcc_params;
+ uint reserved4[2];
+
+#ifdef CONFIG_TEGRA20
+ /* 0x130 */
+ uint reserved4_2[4];
+
+ /* 0x140 */
+ uint usb_cmd;
+ uint usb_sts;
+ uint usb_intr;
+ uint frindex;
+
+ /* 0x150 */
+ uint reserved5;
+ uint periodic_list_base;
+ uint async_list_addr;
+ uint async_tt_sts;
+
+ /* 0x160 */
+ uint burst_size;
+ uint tx_fill_tuning;
+ uint reserved6; /* is this port_sc1 on some controllers? */
+ uint icusb_ctrl;
+
+ /* 0x170 */
+ uint ulpi_viewport;
+ uint reserved7;
+ uint endpt_nak;
+ uint endpt_nak_enable;
+
+ /* 0x180 */
+ uint reserved;
+ uint port_sc1;
+ uint reserved8[6];
+
+ /* 0x1a0 */
+ uint reserved9;
+ uint otgsc;
+ uint usb_mode;
+ uint endpt_setup_stat;
+
+ /* 0x1b0 */
+ uint reserved10[20];
+
+ /* 0x200 */
+ uint reserved11[0x80];
+#else
+ /* 0x130 */
+ uint usb_cmd;
+ uint usb_sts;
+ uint usb_intr;
+ uint frindex;
+
+ /* 0x140 */
+ uint reserved5;
+ uint periodic_list_base;
+ uint async_list_addr;
+ uint reserved5_1;
+
+ /* 0x150 */
+ uint burst_size;
+ uint tx_fill_tuning;
+ uint reserved6;
+ uint icusb_ctrl;
+
+ /* 0x160 */
+ uint ulpi_viewport;
+ uint reserved7[3];
+
+ /* 0x170 */
+ uint reserved;
+ uint port_sc1;
+ uint reserved8[6];
+
+ /* 0x190 */
+ uint reserved9[8];
+
+ /* 0x1b0 */
+ uint reserved10;
+ uint hostpc1_devlc;
+ uint reserved10_1[2];
+
+ /* 0x1c0 */
+ uint reserved10_2[4];
+
+ /* 0x1d0 */
+ uint reserved10_3[4];
+
+ /* 0x1e0 */
+ uint reserved10_4[4];
+
+ /* 0x1f0 */
+ uint reserved10_5;
+ uint otgsc;
+ uint usb_mode;
+ uint reserved10_6;
+
+ /* 0x200 */
+ uint endpt_nak;
+ uint endpt_nak_enable;
+ uint endpt_setup_stat;
+ uint reserved11_1[0x7D];
+#endif
+
+ /* 0x400 */
+ uint susp_ctrl;
+ uint phy_vbus_sensors;
+ uint phy_vbus_wakeup_id;
+ uint phy_alt_vbus_sys;
+
+#ifdef CONFIG_TEGRA20
+ /* 0x410 */
+ uint usb1_legacy_ctrl;
+ uint reserved12[4];
+
+ /* 0x424 */
+ uint ulpi_timing_ctrl_0;
+ uint ulpi_timing_ctrl_1;
+ uint reserved13[53];
+#else
+
+ /* 0x410 */
+ uint usb1_legacy_ctrl;
+ uint reserved12[3];
+
+ /* 0x420 */
+ uint reserved13[56];
+#endif
+
+ /* 0x500 */
+ uint reserved14[64 * 3];
+
+ /* 0x800 */
+ uint utmip_pll_cfg0;
+ uint utmip_pll_cfg1;
+ uint utmip_xcvr_cfg0;
+ uint utmip_bias_cfg0;
+
+ /* 0x810 */
+ uint utmip_hsrx_cfg0;
+ uint utmip_hsrx_cfg1;
+ uint utmip_fslsrx_cfg0;
+ uint utmip_fslsrx_cfg1;
+
+ /* 0x820 */
+ uint utmip_tx_cfg0;
+ uint utmip_misc_cfg0;
+ uint utmip_misc_cfg1;
+ uint utmip_debounce_cfg0;
+
+ /* 0x830 */
+ uint utmip_bat_chrg_cfg0;
+ uint utmip_spare_cfg0;
+ uint utmip_xcvr_cfg1;
+ uint utmip_bias_cfg1;
+};
+
/* USB1_LEGACY_CTRL */
#define USB1_NO_LEGACY_MODE 1
@@ -24,22 +207,46 @@
#define USB_PHY_CLK_VALID (1 << 7)
#define USB_SUSP_CLR (1 << 5)
+#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
/* USB2_IF_USB_SUSP_CTRL_0 */
#define ULPI_PHY_ENB (1 << 13)
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
+#endif
+
/* USBx_UTMIP_MISC_CFG0 */
#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
/* USBx_UTMIP_MISC_CFG1 */
+#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
+
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
#define UTMIP_PLLU_STABLE_COUNT_MASK \
(0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
+/*
+ * Tegra 3 and later: Moved to Clock and Reset register space, see
+ * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
+ */
#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
-#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
/* USBx_UTMIP_PLL_CFG1_0 */
+/* Tegra 3 and later: Moved to Clock and Reset register space */
#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
@@ -91,11 +298,23 @@
/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
#define IC_ENB1 (1 << 3)
-/* PORTSC1, USB1, defined for Tegra20 */
+#ifdef CONFIG_TEGRA20
+/* PORTSC1, USB1 */
#define PTS1_SHIFT 31
#define PTS1_MASK (1 << PTS1_SHIFT)
#define STS1 (1 << 30)
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT 30
+#define PTS_MASK (3U << PTS_SHIFT)
+#define STS (1 << 29)
+#else
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT 29
+#define PTS_MASK (0x7U << PTS_SHIFT)
+#define STS (1 << 28)
+#endif
+
#define PTS_UTMI 0
#define PTS_RESERVED 1
#define PTS_ULPI 2
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index 9c22c08..c1cb3ef 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -1,616 +1,320 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA114_PINMUX_H_
#define _TEGRA114_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
- PINGRP_CLK2_REQ,
- PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- PINGRP_GMI_WP_N,
- PINGRP_GMI_IORDY,
- PINGRP_GMI_WAIT,
- PINGRP_GMI_ADV_N,
- PINGRP_GMI_CLK,
- PINGRP_GMI_CS0_N,
- PINGRP_GMI_CS1_N,
- PINGRP_GMI_CS2_N,
- PINGRP_GMI_CS3_N,
- PINGRP_GMI_CS4_N,
- PINGRP_GMI_CS6_N,
- PINGRP_GMI_CS7_N,
- PINGRP_GMI_AD0,
- PINGRP_GMI_AD1,
- PINGRP_GMI_AD2,
- PINGRP_GMI_AD3,
- PINGRP_GMI_AD4,
- PINGRP_GMI_AD5,
- PINGRP_GMI_AD6,
- PINGRP_GMI_AD7,
- PINGRP_GMI_AD8,
- PINGRP_GMI_AD9,
- PINGRP_GMI_AD10,
- PINGRP_GMI_AD11,
- PINGRP_GMI_AD12,
- PINGRP_GMI_AD13,
- PINGRP_GMI_AD14,
- PINGRP_GMI_AD15,
- PINGRP_GMI_A16,
- PINGRP_GMI_A17,
- PINGRP_GMI_A18,
- PINGRP_GMI_A19,
- PINGRP_GMI_WR_N,
- PINGRP_GMI_OE_N,
- PINGRP_GMI_DQS,
- PINGRP_GMI_RST_N,
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_SYS_CLK_REQ,
- PINGRP_CORE_PWR_REQ,
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_DVFS_PWM,
- PINGRP_GPIO_X1_AUD,
- PINGRP_GPIO_X3_AUD,
- PINGRP_DVFS_CLK,
- PINGRP_GPIO_X4_AUD,
- PINGRP_GPIO_X5_AUD,
- PINGRP_GPIO_X6_AUD,
- PINGRP_GPIO_X7_AUD,
- PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
- PINGRP_SDMMC1_WP_N,
- PINGRP_SDMMC3_CD_N,
- PINGRP_GPIO_W2_AUD,
- PINGRP_GPIO_W3_AUD,
- PINGRP_USB_VBUS_EN0, /* offset 0x33f4 */
- PINGRP_USB_VBUS_EN1,
- PINGRP_SDMMC3_CLK_LB_IN,
- PINGRP_SDMMC3_CLK_LB_OUT,
- PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
- PINGRP_COUNT,
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_GMI_WP_N_PC7,
+ PMUX_PINGRP_GMI_IORDY_PI5,
+ PMUX_PINGRP_GMI_WAIT_PI7,
+ PMUX_PINGRP_GMI_ADV_N_PK0,
+ PMUX_PINGRP_GMI_CLK_PK1,
+ PMUX_PINGRP_GMI_CS0_N_PJ0,
+ PMUX_PINGRP_GMI_CS1_N_PJ2,
+ PMUX_PINGRP_GMI_CS2_N_PK3,
+ PMUX_PINGRP_GMI_CS3_N_PK4,
+ PMUX_PINGRP_GMI_CS4_N_PK2,
+ PMUX_PINGRP_GMI_CS6_N_PI3,
+ PMUX_PINGRP_GMI_CS7_N_PI6,
+ PMUX_PINGRP_GMI_AD0_PG0,
+ PMUX_PINGRP_GMI_AD1_PG1,
+ PMUX_PINGRP_GMI_AD2_PG2,
+ PMUX_PINGRP_GMI_AD3_PG3,
+ PMUX_PINGRP_GMI_AD4_PG4,
+ PMUX_PINGRP_GMI_AD5_PG5,
+ PMUX_PINGRP_GMI_AD6_PG6,
+ PMUX_PINGRP_GMI_AD7_PG7,
+ PMUX_PINGRP_GMI_AD8_PH0,
+ PMUX_PINGRP_GMI_AD9_PH1,
+ PMUX_PINGRP_GMI_AD10_PH2,
+ PMUX_PINGRP_GMI_AD11_PH3,
+ PMUX_PINGRP_GMI_AD12_PH4,
+ PMUX_PINGRP_GMI_AD13_PH5,
+ PMUX_PINGRP_GMI_AD14_PH6,
+ PMUX_PINGRP_GMI_AD15_PH7,
+ PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_PINGRP_GMI_WR_N_PI0,
+ PMUX_PINGRP_GMI_OE_N_PI1,
+ PMUX_PINGRP_GMI_DQS_P_PJ3,
+ PMUX_PINGRP_GMI_RST_N_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+ PMUX_PINGRP_CORE_PWR_REQ,
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_CLK1_REQ_PEE2,
+ PMUX_PINGRP_CLK1_OUT_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_DVFS_PWM_PX0,
+ PMUX_PINGRP_GPIO_X1_AUD_PX1,
+ PMUX_PINGRP_GPIO_X3_AUD_PX3,
+ PMUX_PINGRP_DVFS_CLK_PX2,
+ PMUX_PINGRP_GPIO_X4_AUD_PX4,
+ PMUX_PINGRP_GPIO_X5_AUD_PX5,
+ PMUX_PINGRP_GPIO_X6_AUD_PX6,
+ PMUX_PINGRP_GPIO_X7_AUD_PX7,
+ PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+ PMUX_PINGRP_SDMMC1_WP_N_PV3,
+ PMUX_PINGRP_SDMMC3_CD_N_PV2,
+ PMUX_PINGRP_GPIO_W2_AUD_PW2,
+ PMUX_PINGRP_GPIO_W3_AUD_PW3,
+ PMUX_PINGRP_USB_VBUS_EN0_PN4,
+ PMUX_PINGRP_USB_VBUS_EN1_PN5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+ PMUX_PINGRP_GMI_CLK_LB,
+ PMUX_PINGRP_RESET_OUT_N,
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
- PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
- PDRIVE_PINGROUP_DAP5,
- PDRIVE_PINGROUP_VBUS,
- PDRIVE_PINGROUP_AO3,
- PDRIVE_PINGROUP_HVC,
- PDRIVE_PINGROUP_SDIO4,
- PDRIVE_PINGROUP_AO0,
- PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_DAP1 = (0x28 / 4),
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_DDC = (0x94 / 4),
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GME = (0xa8 / 4),
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_DEV3 = (0xc4 / 4),
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_AT6 = (0x12c / 4),
+ PMUX_DRVGRP_DAP5,
+ PMUX_DRVGRP_USB_VBUS_EN,
+ PMUX_DRVGRP_AO3,
+ PMUX_DRVGRP_HV0,
+ PMUX_DRVGRP_SDIO4,
+ PMUX_DRVGRP_AO0,
+ PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
- PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
- PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
- PMUX_FUNC_HDMI,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
- PMUX_FUNC_KBC,
- PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
- PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
- PMUX_FUNC_OWR,
- PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
- PMUX_FUNC_RTCK,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC2,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI2_ALT,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_UARTE,
- PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- /* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
PMUX_FUNC_CEC,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
+ PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYA_ALT,
+ PMUX_FUNC_DISPLAYB,
PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
+ PMUX_FUNC_IRDA,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_NAND,
PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
- PMUX_FUNC_SATA,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_RESET_OUT_N,
+ PMUX_FUNC_RTCK,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- /* End of Tegra3 MUX selectors */
- PMUX_FUNC_USB,
- PMUX_FUNC_SOC,
- PMUX_FUNC_CPU,
- PMUX_FUNC_CLK,
- PMUX_FUNC_PWRON,
- PMUX_FUNC_PMI,
- PMUX_FUNC_CLDVFS,
- PMUX_FUNC_RESET_OUT_N,
- /* End of Tegra114 MUX selectors */
-
- PMUX_FUNC_SAFE,
- PMUX_FUNC_MAX,
-
- PMUX_FUNC_INVALID = 0x4000,
- PMUX_FUNC_RSVD1 = 0x8000,
- PMUX_FUNC_RSVD2 = 0x8001,
- PMUX_FUNC_RSVD3 = 0x8002,
- PMUX_FUNC_RSVD4 = 0x8003,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
- || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
- && ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
- PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
- PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE -1
-#define PGRP_HSM_NONE PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
- (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
- (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
- (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* t114 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
- enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
- /* VIL/VIH receivers */
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_RSVD1,
+ PMUX_FUNC_RSVD2,
+ PMUX_FUNC_RSVD3,
+ PMUX_FUNC_RSVD4,
+ PMUX_FUNC_COUNT,
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
-#endif /* _TEGRA114_PINMUX_H_ */
+#endif /* _TEGRA114_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra114/usb.h b/arch/arm/include/asm/arch-tegra114/usb.h
deleted file mode 100644
index d46048c..0000000
--- a/arch/arm/include/asm/arch-tegra114/usb.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA114_USB_H_
-#define _TEGRA114_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[2];
-
- /* 0x130 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x140 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint reserved5_1;
-
- /* 0x150 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6;
- uint icusb_ctrl;
-
- /* 0x160 */
- uint ulpi_viewport;
- uint reserved7[3];
-
- /* 0x170 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x190 */
- uint reserved9[8];
-
- /* 0x1b0 */
- uint reserved10;
- uint hostpc1_devlc;
- uint reserved10_1[2];
-
- /* 0x1c0 */
- uint reserved10_2[4];
-
- /* 0x1d0 */
- uint reserved10_3[4];
-
- /* 0x1e0 */
- uint reserved10_4[4];
-
- /* 0x1f0 */
- uint reserved10_5;
- uint otgsc;
- uint usb_mode;
- uint reserved10_6;
-
- /* 0x200 */
- uint endpt_nak;
- uint endpt_nak_enable;
- uint endpt_setup_stat;
- uint reserved11_1[0x7D];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[3];
-
- /* 0x420 */
- uint reserved13[56];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB2D_HOSTPC1_DEVLC_0 */
-#define PTS_SHIFT 29
-#define PTS_MASK (0x7U << PTS_SHIFT)
-
-#define STS (1 << 28)
-#endif /* _TEGRA114_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index 9662e2b..c49801c 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -1,620 +1,342 @@
/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA124_PINMUX_H_
#define _TEGRA124_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
- PINGRP_CLK2_REQ,
- PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
- PINGRP_GPIO_PC7, /* offset 0x31c0 */
- PINGRP_GPIO_PI5,
- PINGRP_GPIO_PI7,
- PINGRP_GPIO_PK0,
- PINGRP_GPIO_PK1,
- PINGRP_GPIO_PJ0,
- PINGRP_GPIO_PJ2,
- PINGRP_GPIO_PK3,
- PINGRP_GPIO_PK4,
- PINGRP_GPIO_PK2,
- PINGRP_GPIO_PI3,
- PINGRP_GPIO_PI6,
- PINGRP_GPIO_PG0,
- PINGRP_GPIO_PG1,
- PINGRP_GPIO_PG2,
- PINGRP_GPIO_PG3,
- PINGRP_GPIO_PG4,
- PINGRP_GPIO_PG5,
- PINGRP_GPIO_PG6,
- PINGRP_GPIO_PG7,
- PINGRP_GPIO_PH0,
- PINGRP_GPIO_PH1,
- PINGRP_GPIO_PH2,
- PINGRP_GPIO_PH3,
- PINGRP_GPIO_PH4,
- PINGRP_GPIO_PH5,
- PINGRP_GPIO_PH6,
- PINGRP_GPIO_PH7,
- PINGRP_GPIO_PJ7,
- PINGRP_GPIO_PB0,
- PINGRP_GPIO_PB1,
- PINGRP_GPIO_PK7,
- PINGRP_GPIO_PI0,
- PINGRP_GPIO_PI1,
- PINGRP_GPIO_PI2,
- PINGRP_GPIO_PI4, /* offset 0x324c */
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_ROW11,
- PINGRP_KB_ROW12,
- PINGRP_KB_ROW13,
- PINGRP_KB_ROW14,
- PINGRP_KB_ROW15,
- PINGRP_KB_COL0, /* offset 0x32fc */
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_DVFS_PWM,
- PINGRP_GPIO_X1_AUD,
- PINGRP_GPIO_X3_AUD,
- PINGRP_DVFS_CLK,
- PINGRP_GPIO_X4_AUD,
- PINGRP_GPIO_X5_AUD,
- PINGRP_GPIO_X6_AUD,
- PINGRP_GPIO_X7_AUD,
- PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
- PINGRP_PEX_L0_CLKREQ,
- PINGRP_PEX_WAKE,
- PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
- PINGRP_PEX_L1_CLKREQ,
- PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
- PINGRP_SDMMC1_WP_N,
- PINGRP_SDMMC3_CD_N,
- PINGRP_GPIO_W2_AUD,
- PINGRP_GPIO_W3_AUD,
- PINGRP_USB_VBUS_EN0,
- PINGRP_USB_VBUS_EN1,
- PINGRP_SDMMC3_CLK_LB_IN,
- PINGRP_SDMMC3_CLK_LB_OUT,
- PINGRP_GMI_CLK_LB,
- PINGRP_RESET_OUT_N,
- PINGRP_KB_ROW16, /* offset 0x340c */
- PINGRP_KB_ROW17,
- PINGRP_USB_VBUS_EN2,
- PINGRP_GPIO_PFF2,
- PINGRP_DP_HPD, /* last reg offset = 0x3430 */
- PINGRP_COUNT,
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_PC7,
+ PMUX_PINGRP_PI5,
+ PMUX_PINGRP_PI7,
+ PMUX_PINGRP_PK0,
+ PMUX_PINGRP_PK1,
+ PMUX_PINGRP_PJ0,
+ PMUX_PINGRP_PJ2,
+ PMUX_PINGRP_PK3,
+ PMUX_PINGRP_PK4,
+ PMUX_PINGRP_PK2,
+ PMUX_PINGRP_PI3,
+ PMUX_PINGRP_PI6,
+ PMUX_PINGRP_PG0,
+ PMUX_PINGRP_PG1,
+ PMUX_PINGRP_PG2,
+ PMUX_PINGRP_PG3,
+ PMUX_PINGRP_PG4,
+ PMUX_PINGRP_PG5,
+ PMUX_PINGRP_PG6,
+ PMUX_PINGRP_PG7,
+ PMUX_PINGRP_PH0,
+ PMUX_PINGRP_PH1,
+ PMUX_PINGRP_PH2,
+ PMUX_PINGRP_PH3,
+ PMUX_PINGRP_PH4,
+ PMUX_PINGRP_PH5,
+ PMUX_PINGRP_PH6,
+ PMUX_PINGRP_PH7,
+ PMUX_PINGRP_PJ7,
+ PMUX_PINGRP_PB0,
+ PMUX_PINGRP_PB1,
+ PMUX_PINGRP_PK7,
+ PMUX_PINGRP_PI0,
+ PMUX_PINGRP_PI1,
+ PMUX_PINGRP_PI2,
+ PMUX_PINGRP_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_ROW11_PS3,
+ PMUX_PINGRP_KB_ROW12_PS4,
+ PMUX_PINGRP_KB_ROW13_PS5,
+ PMUX_PINGRP_KB_ROW14_PS6,
+ PMUX_PINGRP_KB_ROW15_PS7,
+ PMUX_PINGRP_KB_COL0_PQ0,
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
+ PMUX_PINGRP_DAP_MCLK1_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_DVFS_PWM_PX0,
+ PMUX_PINGRP_GPIO_X1_AUD_PX1,
+ PMUX_PINGRP_GPIO_X3_AUD_PX3,
+ PMUX_PINGRP_DVFS_CLK_PX2,
+ PMUX_PINGRP_GPIO_X4_AUD_PX4,
+ PMUX_PINGRP_GPIO_X5_AUD_PX5,
+ PMUX_PINGRP_GPIO_X6_AUD_PX6,
+ PMUX_PINGRP_GPIO_X7_AUD_PX7,
+ PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
+ PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+ PMUX_PINGRP_PEX_WAKE_N_PDD3,
+ PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
+ PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+ PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
+ PMUX_PINGRP_SDMMC1_WP_N_PV3,
+ PMUX_PINGRP_SDMMC3_CD_N_PV2,
+ PMUX_PINGRP_GPIO_W2_AUD_PW2,
+ PMUX_PINGRP_GPIO_W3_AUD_PW3,
+ PMUX_PINGRP_USB_VBUS_EN0_PN4,
+ PMUX_PINGRP_USB_VBUS_EN1_PN5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
+ PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
+ PMUX_PINGRP_GMI_CLK_LB,
+ PMUX_PINGRP_RESET_OUT_N,
+ PMUX_PINGRP_KB_ROW16_PT0,
+ PMUX_PINGRP_KB_ROW17_PT1,
+ PMUX_PINGRP_USB_VBUS_EN2_PFF1,
+ PMUX_PINGRP_PFF2,
+ PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
- PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
- PDRIVE_PINGROUP_DAP5,
- PDRIVE_PINGROUP_VBUS,
- PDRIVE_PINGROUP_AO3,
- PDRIVE_PINGROUP_HVC,
- PDRIVE_PINGROUP_SDIO4,
- PDRIVE_PINGROUP_AO0,
- PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_DAP1 = (0x28 / 4),
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_SDIO3 = (0x48 / 4),
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_DDC = (0x94 / 4),
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GME = (0xa8 / 4),
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_GPV,
+ PMUX_DRVGRP_DEV3,
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_AT6 = (0x12c / 4),
+ PMUX_DRVGRP_DAP5,
+ PMUX_DRVGRP_USB_VBUS_EN,
+ PMUX_DRVGRP_AO3 = (0x140 / 4),
+ PMUX_DRVGRP_AO0 = (0x148 / 4),
+ PMUX_DRVGRP_HV0,
+ PMUX_DRVGRP_SDIO4 = (0x15c / 4),
+ PMUX_DRVGRP_AO4,
+ PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
- PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
- PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
- PMUX_FUNC_HDMI,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
- PMUX_FUNC_KBC,
- PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
- PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
- PMUX_FUNC_OWR,
- PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
- PMUX_FUNC_RTCK,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC2,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI2_ALT,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_UARTE,
- PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- /* End of Tegra2 MUX selectors */
PMUX_FUNC_BLINK,
+ PMUX_FUNC_CCLA,
PMUX_FUNC_CEC,
+ PMUX_FUNC_CLDVFS,
+ PMUX_FUNC_CLK,
PMUX_FUNC_CLK12,
+ PMUX_FUNC_CPU,
PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
+ PMUX_FUNC_DAP1,
+ PMUX_FUNC_DAP2,
PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYA_ALT,
+ PMUX_FUNC_DISPLAYB,
+ PMUX_FUNC_DP,
PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
- PMUX_FUNC_EMC_DLL,
PMUX_FUNC_EXTPERIPH1,
PMUX_FUNC_EXTPERIPH2,
PMUX_FUNC_EXTPERIPH3,
+ PMUX_FUNC_GMI,
PMUX_FUNC_GMI_ALT,
PMUX_FUNC_HDA,
PMUX_FUNC_HSI,
+ PMUX_FUNC_I2C1,
+ PMUX_FUNC_I2C2,
+ PMUX_FUNC_I2C3,
PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
PMUX_FUNC_I2CPWR,
PMUX_FUNC_I2S0,
PMUX_FUNC_I2S1,
PMUX_FUNC_I2S2,
PMUX_FUNC_I2S3,
PMUX_FUNC_I2S4,
- PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
+ PMUX_FUNC_IRDA,
+ PMUX_FUNC_KBC,
+ PMUX_FUNC_OWR,
+ PMUX_FUNC_PE,
+ PMUX_FUNC_PE0,
+ PMUX_FUNC_PE1,
+ PMUX_FUNC_PMI,
PMUX_FUNC_PWM0,
PMUX_FUNC_PWM1,
PMUX_FUNC_PWM2,
PMUX_FUNC_PWM3,
+ PMUX_FUNC_PWRON,
+ PMUX_FUNC_RESET_OUT_N,
+ PMUX_FUNC_RTCK,
PMUX_FUNC_SATA,
+ PMUX_FUNC_SDMMC1,
+ PMUX_FUNC_SDMMC2,
+ PMUX_FUNC_SDMMC3,
+ PMUX_FUNC_SDMMC4,
+ PMUX_FUNC_SOC,
+ PMUX_FUNC_SPDIF,
+ PMUX_FUNC_SPI1,
+ PMUX_FUNC_SPI2,
+ PMUX_FUNC_SPI3,
+ PMUX_FUNC_SPI4,
PMUX_FUNC_SPI5,
PMUX_FUNC_SPI6,
- PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_SYS,
+ PMUX_FUNC_TMDS,
+ PMUX_FUNC_TRACE,
+ PMUX_FUNC_UARTA,
+ PMUX_FUNC_UARTB,
+ PMUX_FUNC_UARTC,
+ PMUX_FUNC_UARTD,
+ PMUX_FUNC_ULPI,
+ PMUX_FUNC_USB,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- /* End of Tegra3 MUX selectors */
- PMUX_FUNC_USB,
- PMUX_FUNC_SOC,
- PMUX_FUNC_CPU,
- PMUX_FUNC_CLK,
- PMUX_FUNC_PWRON,
- PMUX_FUNC_PMI,
- PMUX_FUNC_CLDVFS,
- PMUX_FUNC_RESET_OUT_N,
- /* End of Tegra114 MUX selectors */
-
- PMUX_FUNC_SAFE,
- PMUX_FUNC_MAX,
-
- PMUX_FUNC_INVALID = 0x4000,
- PMUX_FUNC_RSVD1 = 0x8000,
- PMUX_FUNC_RSVD2 = 0x8001,
- PMUX_FUNC_RSVD3 = 0x8002,
- PMUX_FUNC_RSVD4 = 0x8003,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) \
- ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) || \
- (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) \
- (((tristate) >= PMUX_TRI_NORMAL) && \
- ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
- PMUX_PIN_NONE,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-enum pmux_pin_rcv_sel {
- PMUX_PIN_RCV_SEL_DEFAULT = 0,
- PMUX_PIN_RCV_SEL_NORMAL,
- PMUX_PIN_RCV_SEL_HIGH,
-};
-/* return 1 if a pin_rcv_sel_is in range */
-#define pmux_pin_rcv_sel_isvalid(rcv_sel) \
- (((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
- ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-#define PGRP_SCHMT_NONE -1
-#define PGRP_HSM_NONE PGRP_SCHMT_NONE
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
- (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
- (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
- (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* Tegra124 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0[9]; /* ABP_MISC_PP_ offsets 00-20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
- enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
- /* VIL/VIH receivers */
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_VIMCLK2,
+ PMUX_FUNC_VIMCLK2_ALT,
+ PMUX_FUNC_RSVD1,
+ PMUX_FUNC_RSVD2,
+ PMUX_FUNC_RSVD3,
+ PMUX_FUNC_RSVD4,
+ PMUX_FUNC_COUNT,
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_RCV_SEL
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
-#endif /* _TEGRA124_PINMUX_H_ */
+#endif /* _TEGRA124_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/usb.h b/arch/arm/include/asm/arch-tegra124/usb.h
deleted file mode 100644
index 7a2d785..0000000
--- a/arch/arm/include/asm/arch-tegra124/usb.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _TEGRA124_USB_H_
-#define _TEGRA124_USB_H_
-
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[2];
-
- /* 0x130 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x140 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint reserved5_1;
-
- /* 0x150 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6;
- uint icusb_ctrl;
-
- /* 0x160 */
- uint ulpi_viewport;
- uint reserved7;
- uint reserved7_0;
- uint reserved7_1;
-
- /* 0x170 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x190 */
- uint reserved9[8];
-
- /* 0x1b0 */
- uint reserved10;
- uint hostpc1_devlc;
- uint reserved10_1[2];
-
- /* 0x1c0 */
- uint reserved10_2[4];
-
- /* 0x1d0 */
- uint reserved10_3[4];
-
- /* 0x1e0 */
- uint reserved10_4[4];
-
- /* 0x1f0 */
- uint reserved10_5;
- uint otgsc;
- uint usb_mode;
- uint reserved10_6;
-
- /* 0x200 */
- uint endpt_nak;
- uint endpt_nak_enable;
- uint endpt_setup_stat;
- uint reserved11_1[0x7D];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[3];
-
- /* 0x420 */
- uint reserved13[56];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB1_LEGACY_CTRL */
-#define USB1_NO_LEGACY_MODE 1
-
-#define VBUS_SENSE_CTL_SHIFT 1
-#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT)
-#define VBUS_SENSE_CTL_VBUS_WAKEUP 0
-#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1
-#define VBUS_SENSE_CTL_AB_SESS_VLD 2
-#define VBUS_SENSE_CTL_A_SESS_VLD 3
-
-/* USBx_IF_USB_SUSP_CTRL_0 */
-#define UTMIP_PHY_ENB (1 << 12)
-#define UTMIP_RESET (1 << 11)
-#define USB_PHY_CLK_VALID (1 << 7)
-#define USB_SUSP_CLR (1 << 5)
-
-/* USBx_UTMIP_MISC_CFG0 */
-#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
-
-/* USBx_UTMIP_MISC_CFG1 */
-#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30)
-
-/* Moved to Clock and Reset register space */
-#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
-#define UTMIP_PLLU_STABLE_COUNT_MASK \
- (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
-/* Moved to Clock and Reset register space */
-#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18
-#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \
- (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
-
-/* USBx_UTMIP_PLL_CFG1_0 */
-/* Moved to Clock and Reset register space */
-#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
-#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
- (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
-#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
-#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
-
-/* USBx_UTMIP_BIAS_CFG0_0 */
-#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
-#define UTMIP_OTGPD (1 << 11)
-#define UTMIP_BIASPD (1 << 10)
-#define UTMIP_HSDISCON_LEVEL_SHIFT 2
-#define UTMIP_HSDISCON_LEVEL_MASK \
- (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
-#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
-#define UTMIP_HSSQUELCH_LEVEL_MASK \
- (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
-
-/* USBx_UTMIP_BIAS_CFG1_0 */
-#define UTMIP_FORCE_PDTRK_POWERDOWN 1
-#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
-#define UTMIP_BIAS_PDTRK_COUNT_MASK \
- (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
-
-/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
-#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
-#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
-
-/* USBx_UTMIP_TX_CFG0_0 */
-#define UTMIP_FS_PREAMBLE_J (1 << 19)
-
-/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
-#define UTMIP_PD_CHRG 1
-
-/* USBx_UTMIP_SPARE_CFG0_0 */
-#define FUSE_SETUP_SEL (1 << 3)
-
-/* USBx_UTMIP_HSRX_CFG0_0 */
-#define UTMIP_IDLE_WAIT_SHIFT 15
-#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT)
-#define UTMIP_ELASTIC_LIMIT_SHIFT 10
-#define UTMIP_ELASTIC_LIMIT_MASK \
- (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
-
-/* USBx_UTMIP_HSRX_CFG0_1 */
-#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
-#define UTMIP_HS_SYNC_START_DLY_MASK \
- (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
-
-/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
-#define IC_ENB1 (1 << 3)
-
-/* PORTSC1, USB1, defined for Tegra20 to avoid compiling error */
-#define PTS1_SHIFT 31
-#define PTS1_MASK (1 << PTS1_SHIFT)
-#define STS1 (1 << 30)
-
-/* USB2D_HOSTPC1_DEVLC_0 */
-#define PTS_SHIFT 29
-#define PTS_MASK (0x7U << PTS_SHIFT)
-#define PTS_UTMI 0
-#define PTS_RESERVED 1
-#define PTS_ULPI 2
-#define PTS_ICUSB_SER 3
-#define PTS_HSIC 4
-
-#define STS (1 << 28)
-
-/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
-#define WKOC (1 << 22)
-#define WKDS (1 << 21)
-#define WKCN (1 << 20)
-
-/* USBx_UTMIP_XCVR_CFG0_0 */
-#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
-#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
-#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
-#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
-#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
-#define UTMIP_XCVR_HSSLEW_MSB_MASK \
- (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
-#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
-#define UTMIP_XCVR_SETUP_SHIFT 0
-#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
-
-/* USBx_UTMIP_XCVR_CFG1_0 */
-#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
-#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
- (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
-#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
-#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
-#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
-
-/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
-#define VBUS_VLD_STS (1 << 26)
-
-#endif /* _TEGRA124_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/pinmux.h b/arch/arm/include/asm/arch-tegra20/pinmux.h
index 05925df..11c0104 100644
--- a/arch/arm/include/asm/arch-tegra20/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra20/pinmux.h
@@ -5,8 +5,8 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _PINMUX_H_
-#define _PINMUX_H_
+#ifndef _TEGRA20_PINMUX_H_
+#define _TEGRA20_PINMUX_H_
/*
* Pin groups which we adjust. There are three basic attributes of each pin
@@ -18,148 +18,146 @@
*/
enum pmux_pingrp {
/* APB_MISC_PP_TRISTATE_REG_A_0 */
- PINGRP_ATA,
- PINGRP_ATB,
- PINGRP_ATC,
- PINGRP_ATD,
- PINGRP_CDEV1,
- PINGRP_CDEV2,
- PINGRP_CSUS,
- PINGRP_DAP1,
-
- PINGRP_DAP2,
- PINGRP_DAP3,
- PINGRP_DAP4,
- PINGRP_DTA,
- PINGRP_DTB,
- PINGRP_DTC,
- PINGRP_DTD,
- PINGRP_DTE,
-
- PINGRP_GPU,
- PINGRP_GPV,
- PINGRP_I2CP,
- PINGRP_IRTX,
- PINGRP_IRRX,
- PINGRP_KBCB,
- PINGRP_KBCA,
- PINGRP_PMC,
-
- PINGRP_PTA,
- PINGRP_RM,
- PINGRP_KBCE,
- PINGRP_KBCF,
- PINGRP_GMA,
- PINGRP_GMC,
- PINGRP_SDIO1,
- PINGRP_OWC,
+ PMUX_PINGRP_ATA,
+ PMUX_PINGRP_ATB,
+ PMUX_PINGRP_ATC,
+ PMUX_PINGRP_ATD,
+ PMUX_PINGRP_CDEV1,
+ PMUX_PINGRP_CDEV2,
+ PMUX_PINGRP_CSUS,
+ PMUX_PINGRP_DAP1,
+
+ PMUX_PINGRP_DAP2,
+ PMUX_PINGRP_DAP3,
+ PMUX_PINGRP_DAP4,
+ PMUX_PINGRP_DTA,
+ PMUX_PINGRP_DTB,
+ PMUX_PINGRP_DTC,
+ PMUX_PINGRP_DTD,
+ PMUX_PINGRP_DTE,
+
+ PMUX_PINGRP_GPU,
+ PMUX_PINGRP_GPV,
+ PMUX_PINGRP_I2CP,
+ PMUX_PINGRP_IRTX,
+ PMUX_PINGRP_IRRX,
+ PMUX_PINGRP_KBCB,
+ PMUX_PINGRP_KBCA,
+ PMUX_PINGRP_PMC,
+
+ PMUX_PINGRP_PTA,
+ PMUX_PINGRP_RM,
+ PMUX_PINGRP_KBCE,
+ PMUX_PINGRP_KBCF,
+ PMUX_PINGRP_GMA,
+ PMUX_PINGRP_GMC,
+ PMUX_PINGRP_SDIO1,
+ PMUX_PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
- PINGRP_GME,
- PINGRP_SDC,
- PINGRP_SDD,
- PINGRP_RESERVED0,
- PINGRP_SLXA,
- PINGRP_SLXC,
- PINGRP_SLXD,
- PINGRP_SLXK,
-
- PINGRP_SPDI,
- PINGRP_SPDO,
- PINGRP_SPIA,
- PINGRP_SPIB,
- PINGRP_SPIC,
- PINGRP_SPID,
- PINGRP_SPIE,
- PINGRP_SPIF,
-
- PINGRP_SPIG,
- PINGRP_SPIH,
- PINGRP_UAA,
- PINGRP_UAB,
- PINGRP_UAC,
- PINGRP_UAD,
- PINGRP_UCA,
- PINGRP_UCB,
-
- PINGRP_RESERVED1,
- PINGRP_ATE,
- PINGRP_KBCC,
- PINGRP_RESERVED2,
- PINGRP_RESERVED3,
- PINGRP_GMB,
- PINGRP_GMD,
- PINGRP_DDC,
+ PMUX_PINGRP_GME,
+ PMUX_PINGRP_SDC,
+ PMUX_PINGRP_SDD,
+ PMUX_PINGRP_RESERVED0,
+ PMUX_PINGRP_SLXA,
+ PMUX_PINGRP_SLXC,
+ PMUX_PINGRP_SLXD,
+ PMUX_PINGRP_SLXK,
+
+ PMUX_PINGRP_SPDI,
+ PMUX_PINGRP_SPDO,
+ PMUX_PINGRP_SPIA,
+ PMUX_PINGRP_SPIB,
+ PMUX_PINGRP_SPIC,
+ PMUX_PINGRP_SPID,
+ PMUX_PINGRP_SPIE,
+ PMUX_PINGRP_SPIF,
+
+ PMUX_PINGRP_SPIG,
+ PMUX_PINGRP_SPIH,
+ PMUX_PINGRP_UAA,
+ PMUX_PINGRP_UAB,
+ PMUX_PINGRP_UAC,
+ PMUX_PINGRP_UAD,
+ PMUX_PINGRP_UCA,
+ PMUX_PINGRP_UCB,
+
+ PMUX_PINGRP_RESERVED1,
+ PMUX_PINGRP_ATE,
+ PMUX_PINGRP_KBCC,
+ PMUX_PINGRP_RESERVED2,
+ PMUX_PINGRP_RESERVED3,
+ PMUX_PINGRP_GMB,
+ PMUX_PINGRP_GMD,
+ PMUX_PINGRP_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
- PINGRP_LD0,
- PINGRP_LD1,
- PINGRP_LD2,
- PINGRP_LD3,
- PINGRP_LD4,
- PINGRP_LD5,
- PINGRP_LD6,
- PINGRP_LD7,
-
- PINGRP_LD8,
- PINGRP_LD9,
- PINGRP_LD10,
- PINGRP_LD11,
- PINGRP_LD12,
- PINGRP_LD13,
- PINGRP_LD14,
- PINGRP_LD15,
-
- PINGRP_LD16,
- PINGRP_LD17,
- PINGRP_LHP0,
- PINGRP_LHP1,
- PINGRP_LHP2,
- PINGRP_LVP0,
- PINGRP_LVP1,
- PINGRP_HDINT,
-
- PINGRP_LM0,
- PINGRP_LM1,
- PINGRP_LVS,
- PINGRP_LSC0,
- PINGRP_LSC1,
- PINGRP_LSCK,
- PINGRP_LDC,
- PINGRP_LCSN,
+ PMUX_PINGRP_LD0,
+ PMUX_PINGRP_LD1,
+ PMUX_PINGRP_LD2,
+ PMUX_PINGRP_LD3,
+ PMUX_PINGRP_LD4,
+ PMUX_PINGRP_LD5,
+ PMUX_PINGRP_LD6,
+ PMUX_PINGRP_LD7,
+
+ PMUX_PINGRP_LD8,
+ PMUX_PINGRP_LD9,
+ PMUX_PINGRP_LD10,
+ PMUX_PINGRP_LD11,
+ PMUX_PINGRP_LD12,
+ PMUX_PINGRP_LD13,
+ PMUX_PINGRP_LD14,
+ PMUX_PINGRP_LD15,
+
+ PMUX_PINGRP_LD16,
+ PMUX_PINGRP_LD17,
+ PMUX_PINGRP_LHP0,
+ PMUX_PINGRP_LHP1,
+ PMUX_PINGRP_LHP2,
+ PMUX_PINGRP_LVP0,
+ PMUX_PINGRP_LVP1,
+ PMUX_PINGRP_HDINT,
+
+ PMUX_PINGRP_LM0,
+ PMUX_PINGRP_LM1,
+ PMUX_PINGRP_LVS,
+ PMUX_PINGRP_LSC0,
+ PMUX_PINGRP_LSC1,
+ PMUX_PINGRP_LSCK,
+ PMUX_PINGRP_LDC,
+ PMUX_PINGRP_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
- PINGRP_LSPI,
- PINGRP_LSDA,
- PINGRP_LSDI,
- PINGRP_LPW0,
- PINGRP_LPW1,
- PINGRP_LPW2,
- PINGRP_LDI,
- PINGRP_LHS,
-
- PINGRP_LPP,
- PINGRP_RESERVED4,
- PINGRP_KBCD,
- PINGRP_GPU7,
- PINGRP_DTF,
- PINGRP_UDA,
- PINGRP_CRTP,
- PINGRP_SDB,
+ PMUX_PINGRP_LSPI,
+ PMUX_PINGRP_LSDA,
+ PMUX_PINGRP_LSDI,
+ PMUX_PINGRP_LPW0,
+ PMUX_PINGRP_LPW1,
+ PMUX_PINGRP_LPW2,
+ PMUX_PINGRP_LDI,
+ PMUX_PINGRP_LHS,
+
+ PMUX_PINGRP_LPP,
+ PMUX_PINGRP_RESERVED4,
+ PMUX_PINGRP_KBCD,
+ PMUX_PINGRP_GPU7,
+ PMUX_PINGRP_DTF,
+ PMUX_PINGRP_UDA,
+ PMUX_PINGRP_CRTP,
+ PMUX_PINGRP_SDB,
/* these pin groups only have pullup and pull down control */
- PINGRP_FIRST_NO_MUX,
- PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
- PINGRP_DDRC,
- PINGRP_PMCA,
- PINGRP_PMCB,
- PINGRP_PMCC,
- PINGRP_PMCD,
- PINGRP_PMCE,
- PINGRP_XM2C,
- PINGRP_XM2D,
-
- PINGRP_COUNT,
+ PMUX_PINGRP_CK32,
+ PMUX_PINGRP_DDRC,
+ PMUX_PINGRP_PMCA,
+ PMUX_PINGRP_PMCB,
+ PMUX_PINGRP_PMCC,
+ PMUX_PINGRP_PMCD,
+ PMUX_PINGRP_PMCE,
+ PMUX_PINGRP_XM2C,
+ PMUX_PINGRP_XM2D,
+ PMUX_PINGRP_COUNT,
};
/*
@@ -227,111 +225,13 @@ enum pmux_func {
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
- PMUX_FUNC_SAFE,
-
- /* These don't have a name, but can be used in the table */
PMUX_FUNC_RSVD1,
PMUX_FUNC_RSVD2,
PMUX_FUNC_RSVD3,
PMUX_FUNC_RSVD4,
- PMUX_FUNC_RSVD, /* Not valid and should not be used */
-
PMUX_FUNC_COUNT,
-
- PMUX_FUNC_NONE = -1,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \
- (func) != PMUX_FUNC_RSVD)
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
-
- PMUX_VDDIO_NONE
-};
-
-enum {
- PMUX_TRISTATE_REGS = 4,
- PMUX_MUX_REGS = 7,
- PMUX_PULL_REGS = 5,
-};
-
-/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
-
- uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */
- uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */
- uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(const struct pingroup_config *config);
-
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/**
- * Configuure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(const struct pingroup_config *config, int len);
+#include <asm/arch-tegra/pinmux.h>
-#endif /* PINMUX_H */
+#endif /* _TEGRA20_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/usb.h b/arch/arm/include/asm/arch-tegra20/usb.h
deleted file mode 100644
index 3d94cc7..0000000
--- a/arch/arm/include/asm/arch-tegra20/usb.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA20_USB_H_
-#define _TEGRA20_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[6];
-
- /* 0x140 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x150 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint async_tt_sts;
-
- /* 0x160 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6; /* is this port_sc1 on some controllers? */
- uint icusb_ctrl;
-
- /* 0x170 */
- uint ulpi_viewport;
- uint reserved7;
- uint endpt_nak;
- uint endpt_nak_enable;
-
- /* 0x180 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x1a0 */
- uint reserved9;
- uint otgsc;
- uint usb_mode;
- uint endpt_setup_stat;
-
- /* 0x1b0 */
- uint reserved10[20];
-
- /* 0x200 */
- uint reserved11[0x80];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[4];
-
- /* 0x424 */
- uint ulpi_timing_ctrl_0;
- uint ulpi_timing_ctrl_1;
- uint reserved13[53];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB2_IF_ULPI_TIMING_CTRL_0 */
-#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
-#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
-
-/* USB2_IF_ULPI_TIMING_CTRL_1 */
-#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
-#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
-#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
-#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
-#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
-#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
-
-/* PORTSC, USB2, USB3 */
-#define PTS_SHIFT 30
-#define PTS_MASK (3U << PTS_SHIFT)
-
-#define STS (1 << 29)
-#endif /* _TEGRA20_USB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index a9e1b46..6d83061 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -1,668 +1,397 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA30_PINMUX_H_
#define _TEGRA30_PINMUX_H_
-/*
- * Pin groups which we adjust. There are three basic attributes of each pin
- * group which use this enum:
- *
- * - function
- * - pullup / pulldown
- * - tristate or normal
- */
enum pmux_pingrp {
- PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
- PINGRP_ULPI_DATA1,
- PINGRP_ULPI_DATA2,
- PINGRP_ULPI_DATA3,
- PINGRP_ULPI_DATA4,
- PINGRP_ULPI_DATA5,
- PINGRP_ULPI_DATA6,
- PINGRP_ULPI_DATA7,
- PINGRP_ULPI_CLK,
- PINGRP_ULPI_DIR,
- PINGRP_ULPI_NXT,
- PINGRP_ULPI_STP,
- PINGRP_DAP3_FS,
- PINGRP_DAP3_DIN,
- PINGRP_DAP3_DOUT,
- PINGRP_DAP3_SCLK,
- PINGRP_GPIO_PV0,
- PINGRP_GPIO_PV1,
- PINGRP_SDMMC1_CLK,
- PINGRP_SDMMC1_CMD,
- PINGRP_SDMMC1_DAT3,
- PINGRP_SDMMC1_DAT2,
- PINGRP_SDMMC1_DAT1,
- PINGRP_SDMMC1_DAT0,
- PINGRP_GPIO_PV2,
- PINGRP_GPIO_PV3,
- PINGRP_CLK2_OUT,
- PINGRP_CLK2_REQ,
- PINGRP_LCD_PWR1,
- PINGRP_LCD_PWR2,
- PINGRP_LCD_SDIN,
- PINGRP_LCD_SDOUT,
- PINGRP_LCD_WR_N,
- PINGRP_LCD_CS0_N,
- PINGRP_LCD_DC0,
- PINGRP_LCD_SCK,
- PINGRP_LCD_PWR0,
- PINGRP_LCD_PCLK,
- PINGRP_LCD_DE,
- PINGRP_LCD_HSYNC,
- PINGRP_LCD_VSYNC,
- PINGRP_LCD_D0,
- PINGRP_LCD_D1,
- PINGRP_LCD_D2,
- PINGRP_LCD_D3,
- PINGRP_LCD_D4,
- PINGRP_LCD_D5,
- PINGRP_LCD_D6,
- PINGRP_LCD_D7,
- PINGRP_LCD_D8,
- PINGRP_LCD_D9,
- PINGRP_LCD_D10,
- PINGRP_LCD_D11,
- PINGRP_LCD_D12,
- PINGRP_LCD_D13,
- PINGRP_LCD_D14,
- PINGRP_LCD_D15,
- PINGRP_LCD_D16,
- PINGRP_LCD_D17,
- PINGRP_LCD_D18,
- PINGRP_LCD_D19,
- PINGRP_LCD_D20,
- PINGRP_LCD_D21,
- PINGRP_LCD_D22,
- PINGRP_LCD_D23,
- PINGRP_LCD_CS1_N,
- PINGRP_LCD_M1,
- PINGRP_LCD_DC1,
- PINGRP_HDMI_INT,
- PINGRP_DDC_SCL,
- PINGRP_DDC_SDA,
- PINGRP_CRT_HSYNC,
- PINGRP_CRT_VSYNC,
- PINGRP_VI_D0,
- PINGRP_VI_D1,
- PINGRP_VI_D2,
- PINGRP_VI_D3,
- PINGRP_VI_D4,
- PINGRP_VI_D5,
- PINGRP_VI_D6,
- PINGRP_VI_D7,
- PINGRP_VI_D8,
- PINGRP_VI_D9,
- PINGRP_VI_D10,
- PINGRP_VI_D11,
- PINGRP_VI_PCLK,
- PINGRP_VI_MCLK,
- PINGRP_VI_VSYNC,
- PINGRP_VI_HSYNC,
- PINGRP_UART2_RXD,
- PINGRP_UART2_TXD,
- PINGRP_UART2_RTS_N,
- PINGRP_UART2_CTS_N,
- PINGRP_UART3_TXD,
- PINGRP_UART3_RXD,
- PINGRP_UART3_CTS_N,
- PINGRP_UART3_RTS_N,
- PINGRP_GPIO_PU0,
- PINGRP_GPIO_PU1,
- PINGRP_GPIO_PU2,
- PINGRP_GPIO_PU3,
- PINGRP_GPIO_PU4,
- PINGRP_GPIO_PU5,
- PINGRP_GPIO_PU6,
- PINGRP_GEN1_I2C_SDA,
- PINGRP_GEN1_I2C_SCL,
- PINGRP_DAP4_FS,
- PINGRP_DAP4_DIN,
- PINGRP_DAP4_DOUT,
- PINGRP_DAP4_SCLK,
- PINGRP_CLK3_OUT,
- PINGRP_CLK3_REQ,
- PINGRP_GMI_WP_N,
- PINGRP_GMI_IORDY,
- PINGRP_GMI_WAIT,
- PINGRP_GMI_ADV_N,
- PINGRP_GMI_CLK,
- PINGRP_GMI_CS0_N,
- PINGRP_GMI_CS1_N,
- PINGRP_GMI_CS2_N,
- PINGRP_GMI_CS3_N,
- PINGRP_GMI_CS4_N,
- PINGRP_GMI_CS6_N,
- PINGRP_GMI_CS7_N,
- PINGRP_GMI_AD0,
- PINGRP_GMI_AD1,
- PINGRP_GMI_AD2,
- PINGRP_GMI_AD3,
- PINGRP_GMI_AD4,
- PINGRP_GMI_AD5,
- PINGRP_GMI_AD6,
- PINGRP_GMI_AD7,
- PINGRP_GMI_AD8,
- PINGRP_GMI_AD9,
- PINGRP_GMI_AD10,
- PINGRP_GMI_AD11,
- PINGRP_GMI_AD12,
- PINGRP_GMI_AD13,
- PINGRP_GMI_AD14,
- PINGRP_GMI_AD15,
- PINGRP_GMI_A16,
- PINGRP_GMI_A17,
- PINGRP_GMI_A18,
- PINGRP_GMI_A19,
- PINGRP_GMI_WR_N,
- PINGRP_GMI_OE_N,
- PINGRP_GMI_DQS,
- PINGRP_GMI_RST_N,
- PINGRP_GEN2_I2C_SCL,
- PINGRP_GEN2_I2C_SDA,
- PINGRP_SDMMC4_CLK,
- PINGRP_SDMMC4_CMD,
- PINGRP_SDMMC4_DAT0,
- PINGRP_SDMMC4_DAT1,
- PINGRP_SDMMC4_DAT2,
- PINGRP_SDMMC4_DAT3,
- PINGRP_SDMMC4_DAT4,
- PINGRP_SDMMC4_DAT5,
- PINGRP_SDMMC4_DAT6,
- PINGRP_SDMMC4_DAT7,
- PINGRP_SDMMC4_RST_N,
- PINGRP_CAM_MCLK,
- PINGRP_GPIO_PCC1,
- PINGRP_GPIO_PBB0,
- PINGRP_CAM_I2C_SCL,
- PINGRP_CAM_I2C_SDA,
- PINGRP_GPIO_PBB3,
- PINGRP_GPIO_PBB4,
- PINGRP_GPIO_PBB5,
- PINGRP_GPIO_PBB6,
- PINGRP_GPIO_PBB7,
- PINGRP_GPIO_PCC2,
- PINGRP_JTAG_RTCK,
- PINGRP_PWR_I2C_SCL,
- PINGRP_PWR_I2C_SDA,
- PINGRP_KB_ROW0,
- PINGRP_KB_ROW1,
- PINGRP_KB_ROW2,
- PINGRP_KB_ROW3,
- PINGRP_KB_ROW4,
- PINGRP_KB_ROW5,
- PINGRP_KB_ROW6,
- PINGRP_KB_ROW7,
- PINGRP_KB_ROW8,
- PINGRP_KB_ROW9,
- PINGRP_KB_ROW10,
- PINGRP_KB_ROW11,
- PINGRP_KB_ROW12,
- PINGRP_KB_ROW13,
- PINGRP_KB_ROW14,
- PINGRP_KB_ROW15,
- PINGRP_KB_COL0,
- PINGRP_KB_COL1,
- PINGRP_KB_COL2,
- PINGRP_KB_COL3,
- PINGRP_KB_COL4,
- PINGRP_KB_COL5,
- PINGRP_KB_COL6,
- PINGRP_KB_COL7,
- PINGRP_CLK_32K_OUT,
- PINGRP_SYS_CLK_REQ,
- PINGRP_CORE_PWR_REQ,
- PINGRP_CPU_PWR_REQ,
- PINGRP_PWR_INT_N,
- PINGRP_CLK_32K_IN,
- PINGRP_OWR,
- PINGRP_DAP1_FS,
- PINGRP_DAP1_DIN,
- PINGRP_DAP1_DOUT,
- PINGRP_DAP1_SCLK,
- PINGRP_CLK1_REQ,
- PINGRP_CLK1_OUT,
- PINGRP_SPDIF_IN,
- PINGRP_SPDIF_OUT,
- PINGRP_DAP2_FS,
- PINGRP_DAP2_DIN,
- PINGRP_DAP2_DOUT,
- PINGRP_DAP2_SCLK,
- PINGRP_SPI2_MOSI,
- PINGRP_SPI2_MISO,
- PINGRP_SPI2_CS0_N,
- PINGRP_SPI2_SCK,
- PINGRP_SPI1_MOSI,
- PINGRP_SPI1_SCK,
- PINGRP_SPI1_CS0_N,
- PINGRP_SPI1_MISO,
- PINGRP_SPI2_CS1_N,
- PINGRP_SPI2_CS2_N,
- PINGRP_SDMMC3_CLK,
- PINGRP_SDMMC3_CMD,
- PINGRP_SDMMC3_DAT0,
- PINGRP_SDMMC3_DAT1,
- PINGRP_SDMMC3_DAT2,
- PINGRP_SDMMC3_DAT3,
- PINGRP_SDMMC3_DAT4,
- PINGRP_SDMMC3_DAT5,
- PINGRP_SDMMC3_DAT6,
- PINGRP_SDMMC3_DAT7,
- PINGRP_PEX_L0_PRSNT_N,
- PINGRP_PEX_L0_RST_N,
- PINGRP_PEX_L0_CLKREQ_N,
- PINGRP_PEX_WAKE_N,
- PINGRP_PEX_L1_PRSNT_N,
- PINGRP_PEX_L1_RST_N,
- PINGRP_PEX_L1_CLKREQ_N,
- PINGRP_PEX_L2_PRSNT_N,
- PINGRP_PEX_L2_RST_N,
- PINGRP_PEX_L2_CLKREQ_N,
- PINGRP_HDMI_CEC, /* offset 0x33e0 */
- PINGRP_COUNT,
+ PMUX_PINGRP_ULPI_DATA0_PO1,
+ PMUX_PINGRP_ULPI_DATA1_PO2,
+ PMUX_PINGRP_ULPI_DATA2_PO3,
+ PMUX_PINGRP_ULPI_DATA3_PO4,
+ PMUX_PINGRP_ULPI_DATA4_PO5,
+ PMUX_PINGRP_ULPI_DATA5_PO6,
+ PMUX_PINGRP_ULPI_DATA6_PO7,
+ PMUX_PINGRP_ULPI_DATA7_PO0,
+ PMUX_PINGRP_ULPI_CLK_PY0,
+ PMUX_PINGRP_ULPI_DIR_PY1,
+ PMUX_PINGRP_ULPI_NXT_PY2,
+ PMUX_PINGRP_ULPI_STP_PY3,
+ PMUX_PINGRP_DAP3_FS_PP0,
+ PMUX_PINGRP_DAP3_DIN_PP1,
+ PMUX_PINGRP_DAP3_DOUT_PP2,
+ PMUX_PINGRP_DAP3_SCLK_PP3,
+ PMUX_PINGRP_PV0,
+ PMUX_PINGRP_PV1,
+ PMUX_PINGRP_SDMMC1_CLK_PZ0,
+ PMUX_PINGRP_SDMMC1_CMD_PZ1,
+ PMUX_PINGRP_SDMMC1_DAT3_PY4,
+ PMUX_PINGRP_SDMMC1_DAT2_PY5,
+ PMUX_PINGRP_SDMMC1_DAT1_PY6,
+ PMUX_PINGRP_SDMMC1_DAT0_PY7,
+ PMUX_PINGRP_PV2,
+ PMUX_PINGRP_PV3,
+ PMUX_PINGRP_CLK2_OUT_PW5,
+ PMUX_PINGRP_CLK2_REQ_PCC5,
+ PMUX_PINGRP_LCD_PWR1_PC1,
+ PMUX_PINGRP_LCD_PWR2_PC6,
+ PMUX_PINGRP_LCD_SDIN_PZ2,
+ PMUX_PINGRP_LCD_SDOUT_PN5,
+ PMUX_PINGRP_LCD_WR_N_PZ3,
+ PMUX_PINGRP_LCD_CS0_N_PN4,
+ PMUX_PINGRP_LCD_DC0_PN6,
+ PMUX_PINGRP_LCD_SCK_PZ4,
+ PMUX_PINGRP_LCD_PWR0_PB2,
+ PMUX_PINGRP_LCD_PCLK_PB3,
+ PMUX_PINGRP_LCD_DE_PJ1,
+ PMUX_PINGRP_LCD_HSYNC_PJ3,
+ PMUX_PINGRP_LCD_VSYNC_PJ4,
+ PMUX_PINGRP_LCD_D0_PE0,
+ PMUX_PINGRP_LCD_D1_PE1,
+ PMUX_PINGRP_LCD_D2_PE2,
+ PMUX_PINGRP_LCD_D3_PE3,
+ PMUX_PINGRP_LCD_D4_PE4,
+ PMUX_PINGRP_LCD_D5_PE5,
+ PMUX_PINGRP_LCD_D6_PE6,
+ PMUX_PINGRP_LCD_D7_PE7,
+ PMUX_PINGRP_LCD_D8_PF0,
+ PMUX_PINGRP_LCD_D9_PF1,
+ PMUX_PINGRP_LCD_D10_PF2,
+ PMUX_PINGRP_LCD_D11_PF3,
+ PMUX_PINGRP_LCD_D12_PF4,
+ PMUX_PINGRP_LCD_D13_PF5,
+ PMUX_PINGRP_LCD_D14_PF6,
+ PMUX_PINGRP_LCD_D15_PF7,
+ PMUX_PINGRP_LCD_D16_PM0,
+ PMUX_PINGRP_LCD_D17_PM1,
+ PMUX_PINGRP_LCD_D18_PM2,
+ PMUX_PINGRP_LCD_D19_PM3,
+ PMUX_PINGRP_LCD_D20_PM4,
+ PMUX_PINGRP_LCD_D21_PM5,
+ PMUX_PINGRP_LCD_D22_PM6,
+ PMUX_PINGRP_LCD_D23_PM7,
+ PMUX_PINGRP_LCD_CS1_N_PW0,
+ PMUX_PINGRP_LCD_M1_PW1,
+ PMUX_PINGRP_LCD_DC1_PD2,
+ PMUX_PINGRP_HDMI_INT_PN7,
+ PMUX_PINGRP_DDC_SCL_PV4,
+ PMUX_PINGRP_DDC_SDA_PV5,
+ PMUX_PINGRP_CRT_HSYNC_PV6,
+ PMUX_PINGRP_CRT_VSYNC_PV7,
+ PMUX_PINGRP_VI_D0_PT4,
+ PMUX_PINGRP_VI_D1_PD5,
+ PMUX_PINGRP_VI_D2_PL0,
+ PMUX_PINGRP_VI_D3_PL1,
+ PMUX_PINGRP_VI_D4_PL2,
+ PMUX_PINGRP_VI_D5_PL3,
+ PMUX_PINGRP_VI_D6_PL4,
+ PMUX_PINGRP_VI_D7_PL5,
+ PMUX_PINGRP_VI_D8_PL6,
+ PMUX_PINGRP_VI_D9_PL7,
+ PMUX_PINGRP_VI_D10_PT2,
+ PMUX_PINGRP_VI_D11_PT3,
+ PMUX_PINGRP_VI_PCLK_PT0,
+ PMUX_PINGRP_VI_MCLK_PT1,
+ PMUX_PINGRP_VI_VSYNC_PD6,
+ PMUX_PINGRP_VI_HSYNC_PD7,
+ PMUX_PINGRP_UART2_RXD_PC3,
+ PMUX_PINGRP_UART2_TXD_PC2,
+ PMUX_PINGRP_UART2_RTS_N_PJ6,
+ PMUX_PINGRP_UART2_CTS_N_PJ5,
+ PMUX_PINGRP_UART3_TXD_PW6,
+ PMUX_PINGRP_UART3_RXD_PW7,
+ PMUX_PINGRP_UART3_CTS_N_PA1,
+ PMUX_PINGRP_UART3_RTS_N_PC0,
+ PMUX_PINGRP_PU0,
+ PMUX_PINGRP_PU1,
+ PMUX_PINGRP_PU2,
+ PMUX_PINGRP_PU3,
+ PMUX_PINGRP_PU4,
+ PMUX_PINGRP_PU5,
+ PMUX_PINGRP_PU6,
+ PMUX_PINGRP_GEN1_I2C_SDA_PC5,
+ PMUX_PINGRP_GEN1_I2C_SCL_PC4,
+ PMUX_PINGRP_DAP4_FS_PP4,
+ PMUX_PINGRP_DAP4_DIN_PP5,
+ PMUX_PINGRP_DAP4_DOUT_PP6,
+ PMUX_PINGRP_DAP4_SCLK_PP7,
+ PMUX_PINGRP_CLK3_OUT_PEE0,
+ PMUX_PINGRP_CLK3_REQ_PEE1,
+ PMUX_PINGRP_GMI_WP_N_PC7,
+ PMUX_PINGRP_GMI_IORDY_PI5,
+ PMUX_PINGRP_GMI_WAIT_PI7,
+ PMUX_PINGRP_GMI_ADV_N_PK0,
+ PMUX_PINGRP_GMI_CLK_PK1,
+ PMUX_PINGRP_GMI_CS0_N_PJ0,
+ PMUX_PINGRP_GMI_CS1_N_PJ2,
+ PMUX_PINGRP_GMI_CS2_N_PK3,
+ PMUX_PINGRP_GMI_CS3_N_PK4,
+ PMUX_PINGRP_GMI_CS4_N_PK2,
+ PMUX_PINGRP_GMI_CS6_N_PI3,
+ PMUX_PINGRP_GMI_CS7_N_PI6,
+ PMUX_PINGRP_GMI_AD0_PG0,
+ PMUX_PINGRP_GMI_AD1_PG1,
+ PMUX_PINGRP_GMI_AD2_PG2,
+ PMUX_PINGRP_GMI_AD3_PG3,
+ PMUX_PINGRP_GMI_AD4_PG4,
+ PMUX_PINGRP_GMI_AD5_PG5,
+ PMUX_PINGRP_GMI_AD6_PG6,
+ PMUX_PINGRP_GMI_AD7_PG7,
+ PMUX_PINGRP_GMI_AD8_PH0,
+ PMUX_PINGRP_GMI_AD9_PH1,
+ PMUX_PINGRP_GMI_AD10_PH2,
+ PMUX_PINGRP_GMI_AD11_PH3,
+ PMUX_PINGRP_GMI_AD12_PH4,
+ PMUX_PINGRP_GMI_AD13_PH5,
+ PMUX_PINGRP_GMI_AD14_PH6,
+ PMUX_PINGRP_GMI_AD15_PH7,
+ PMUX_PINGRP_GMI_A16_PJ7,
+ PMUX_PINGRP_GMI_A17_PB0,
+ PMUX_PINGRP_GMI_A18_PB1,
+ PMUX_PINGRP_GMI_A19_PK7,
+ PMUX_PINGRP_GMI_WR_N_PI0,
+ PMUX_PINGRP_GMI_OE_N_PI1,
+ PMUX_PINGRP_GMI_DQS_PI2,
+ PMUX_PINGRP_GMI_RST_N_PI4,
+ PMUX_PINGRP_GEN2_I2C_SCL_PT5,
+ PMUX_PINGRP_GEN2_I2C_SDA_PT6,
+ PMUX_PINGRP_SDMMC4_CLK_PCC4,
+ PMUX_PINGRP_SDMMC4_CMD_PT7,
+ PMUX_PINGRP_SDMMC4_DAT0_PAA0,
+ PMUX_PINGRP_SDMMC4_DAT1_PAA1,
+ PMUX_PINGRP_SDMMC4_DAT2_PAA2,
+ PMUX_PINGRP_SDMMC4_DAT3_PAA3,
+ PMUX_PINGRP_SDMMC4_DAT4_PAA4,
+ PMUX_PINGRP_SDMMC4_DAT5_PAA5,
+ PMUX_PINGRP_SDMMC4_DAT6_PAA6,
+ PMUX_PINGRP_SDMMC4_DAT7_PAA7,
+ PMUX_PINGRP_SDMMC4_RST_N_PCC3,
+ PMUX_PINGRP_CAM_MCLK_PCC0,
+ PMUX_PINGRP_PCC1,
+ PMUX_PINGRP_PBB0,
+ PMUX_PINGRP_CAM_I2C_SCL_PBB1,
+ PMUX_PINGRP_CAM_I2C_SDA_PBB2,
+ PMUX_PINGRP_PBB3,
+ PMUX_PINGRP_PBB4,
+ PMUX_PINGRP_PBB5,
+ PMUX_PINGRP_PBB6,
+ PMUX_PINGRP_PBB7,
+ PMUX_PINGRP_PCC2,
+ PMUX_PINGRP_JTAG_RTCK_PU7,
+ PMUX_PINGRP_PWR_I2C_SCL_PZ6,
+ PMUX_PINGRP_PWR_I2C_SDA_PZ7,
+ PMUX_PINGRP_KB_ROW0_PR0,
+ PMUX_PINGRP_KB_ROW1_PR1,
+ PMUX_PINGRP_KB_ROW2_PR2,
+ PMUX_PINGRP_KB_ROW3_PR3,
+ PMUX_PINGRP_KB_ROW4_PR4,
+ PMUX_PINGRP_KB_ROW5_PR5,
+ PMUX_PINGRP_KB_ROW6_PR6,
+ PMUX_PINGRP_KB_ROW7_PR7,
+ PMUX_PINGRP_KB_ROW8_PS0,
+ PMUX_PINGRP_KB_ROW9_PS1,
+ PMUX_PINGRP_KB_ROW10_PS2,
+ PMUX_PINGRP_KB_ROW11_PS3,
+ PMUX_PINGRP_KB_ROW12_PS4,
+ PMUX_PINGRP_KB_ROW13_PS5,
+ PMUX_PINGRP_KB_ROW14_PS6,
+ PMUX_PINGRP_KB_ROW15_PS7,
+ PMUX_PINGRP_KB_COL0_PQ0,
+ PMUX_PINGRP_KB_COL1_PQ1,
+ PMUX_PINGRP_KB_COL2_PQ2,
+ PMUX_PINGRP_KB_COL3_PQ3,
+ PMUX_PINGRP_KB_COL4_PQ4,
+ PMUX_PINGRP_KB_COL5_PQ5,
+ PMUX_PINGRP_KB_COL6_PQ6,
+ PMUX_PINGRP_KB_COL7_PQ7,
+ PMUX_PINGRP_CLK_32K_OUT_PA0,
+ PMUX_PINGRP_SYS_CLK_REQ_PZ5,
+ PMUX_PINGRP_CORE_PWR_REQ,
+ PMUX_PINGRP_CPU_PWR_REQ,
+ PMUX_PINGRP_PWR_INT_N,
+ PMUX_PINGRP_CLK_32K_IN,
+ PMUX_PINGRP_OWR,
+ PMUX_PINGRP_DAP1_FS_PN0,
+ PMUX_PINGRP_DAP1_DIN_PN1,
+ PMUX_PINGRP_DAP1_DOUT_PN2,
+ PMUX_PINGRP_DAP1_SCLK_PN3,
+ PMUX_PINGRP_CLK1_REQ_PEE2,
+ PMUX_PINGRP_CLK1_OUT_PW4,
+ PMUX_PINGRP_SPDIF_IN_PK6,
+ PMUX_PINGRP_SPDIF_OUT_PK5,
+ PMUX_PINGRP_DAP2_FS_PA2,
+ PMUX_PINGRP_DAP2_DIN_PA4,
+ PMUX_PINGRP_DAP2_DOUT_PA5,
+ PMUX_PINGRP_DAP2_SCLK_PA3,
+ PMUX_PINGRP_SPI2_MOSI_PX0,
+ PMUX_PINGRP_SPI2_MISO_PX1,
+ PMUX_PINGRP_SPI2_CS0_N_PX3,
+ PMUX_PINGRP_SPI2_SCK_PX2,
+ PMUX_PINGRP_SPI1_MOSI_PX4,
+ PMUX_PINGRP_SPI1_SCK_PX5,
+ PMUX_PINGRP_SPI1_CS0_N_PX6,
+ PMUX_PINGRP_SPI1_MISO_PX7,
+ PMUX_PINGRP_SPI2_CS1_N_PW2,
+ PMUX_PINGRP_SPI2_CS2_N_PW3,
+ PMUX_PINGRP_SDMMC3_CLK_PA6,
+ PMUX_PINGRP_SDMMC3_CMD_PA7,
+ PMUX_PINGRP_SDMMC3_DAT0_PB7,
+ PMUX_PINGRP_SDMMC3_DAT1_PB6,
+ PMUX_PINGRP_SDMMC3_DAT2_PB5,
+ PMUX_PINGRP_SDMMC3_DAT3_PB4,
+ PMUX_PINGRP_SDMMC3_DAT4_PD1,
+ PMUX_PINGRP_SDMMC3_DAT5_PD0,
+ PMUX_PINGRP_SDMMC3_DAT6_PD3,
+ PMUX_PINGRP_SDMMC3_DAT7_PD4,
+ PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
+ PMUX_PINGRP_PEX_L0_RST_N_PDD1,
+ PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
+ PMUX_PINGRP_PEX_WAKE_N_PDD3,
+ PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
+ PMUX_PINGRP_PEX_L1_RST_N_PDD5,
+ PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
+ PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
+ PMUX_PINGRP_PEX_L2_RST_N_PCC6,
+ PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
+ PMUX_PINGRP_HDMI_CEC_PEE3,
+ PMUX_PINGRP_COUNT,
};
-enum pdrive_pingrp {
- PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
- PDRIVE_PINGROUP_AO2,
- PDRIVE_PINGROUP_AT1,
- PDRIVE_PINGROUP_AT2,
- PDRIVE_PINGROUP_AT3,
- PDRIVE_PINGROUP_AT4,
- PDRIVE_PINGROUP_AT5,
- PDRIVE_PINGROUP_CDEV1,
- PDRIVE_PINGROUP_CDEV2,
- PDRIVE_PINGROUP_CSUS,
- PDRIVE_PINGROUP_DAP1,
- PDRIVE_PINGROUP_DAP2,
- PDRIVE_PINGROUP_DAP3,
- PDRIVE_PINGROUP_DAP4,
- PDRIVE_PINGROUP_DBG,
- PDRIVE_PINGROUP_LCD1,
- PDRIVE_PINGROUP_LCD2,
- PDRIVE_PINGROUP_SDIO2,
- PDRIVE_PINGROUP_SDIO3,
- PDRIVE_PINGROUP_SPI,
- PDRIVE_PINGROUP_UAA,
- PDRIVE_PINGROUP_UAB,
- PDRIVE_PINGROUP_UART2,
- PDRIVE_PINGROUP_UART3,
- PDRIVE_PINGROUP_VI1 = 24, /* offset 0x8c8 */
- PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8ec */
- PDRIVE_PINGROUP_CRT = 36, /* offset 0x8f8 */
- PDRIVE_PINGROUP_DDC,
- PDRIVE_PINGROUP_GMA,
- PDRIVE_PINGROUP_GMB,
- PDRIVE_PINGROUP_GMC,
- PDRIVE_PINGROUP_GMD,
- PDRIVE_PINGROUP_GME,
- PDRIVE_PINGROUP_GMF,
- PDRIVE_PINGROUP_GMG,
- PDRIVE_PINGROUP_GMH,
- PDRIVE_PINGROUP_OWR,
- PDRIVE_PINGROUP_UAD,
- PDRIVE_PINGROUP_GPV,
- PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
- PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
- PDRIVE_PINGROUP_COUNT,
+enum pmux_drvgrp {
+ PMUX_DRVGRP_AO1,
+ PMUX_DRVGRP_AO2,
+ PMUX_DRVGRP_AT1,
+ PMUX_DRVGRP_AT2,
+ PMUX_DRVGRP_AT3,
+ PMUX_DRVGRP_AT4,
+ PMUX_DRVGRP_AT5,
+ PMUX_DRVGRP_CDEV1,
+ PMUX_DRVGRP_CDEV2,
+ PMUX_DRVGRP_CSUS,
+ PMUX_DRVGRP_DAP1,
+ PMUX_DRVGRP_DAP2,
+ PMUX_DRVGRP_DAP3,
+ PMUX_DRVGRP_DAP4,
+ PMUX_DRVGRP_DBG,
+ PMUX_DRVGRP_LCD1,
+ PMUX_DRVGRP_LCD2,
+ PMUX_DRVGRP_SDIO2,
+ PMUX_DRVGRP_SDIO3,
+ PMUX_DRVGRP_SPI,
+ PMUX_DRVGRP_UAA,
+ PMUX_DRVGRP_UAB,
+ PMUX_DRVGRP_UART2,
+ PMUX_DRVGRP_UART3,
+ PMUX_DRVGRP_VI1,
+ PMUX_DRVGRP_SDIO1 = (0x84 / 4),
+ PMUX_DRVGRP_CRT = (0x90 / 4),
+ PMUX_DRVGRP_DDC,
+ PMUX_DRVGRP_GMA,
+ PMUX_DRVGRP_GMB,
+ PMUX_DRVGRP_GMC,
+ PMUX_DRVGRP_GMD,
+ PMUX_DRVGRP_GME,
+ PMUX_DRVGRP_GMF,
+ PMUX_DRVGRP_GMG,
+ PMUX_DRVGRP_GMH,
+ PMUX_DRVGRP_OWR,
+ PMUX_DRVGRP_UDA,
+ PMUX_DRVGRP_GPV,
+ PMUX_DRVGRP_DEV3,
+ PMUX_DRVGRP_CEC = (0xd0 / 4),
+ PMUX_DRVGRP_COUNT,
};
-/*
- * Functions which can be assigned to each of the pin groups. The values here
- * bear no relation to the values programmed into pinmux registers and are
- * purely a convenience. The translation is done through a table search.
- */
enum pmux_func {
- PMUX_FUNC_AHB_CLK,
- PMUX_FUNC_APB_CLK,
- PMUX_FUNC_AUDIO_SYNC,
+ PMUX_FUNC_BLINK,
+ PMUX_FUNC_CEC,
+ PMUX_FUNC_CLK_12M_OUT,
+ PMUX_FUNC_CLK_32K_IN,
+ PMUX_FUNC_CORE_PWR_REQ,
+ PMUX_FUNC_CPU_PWR_REQ,
PMUX_FUNC_CRT,
- PMUX_FUNC_DAP1,
- PMUX_FUNC_DAP2,
- PMUX_FUNC_DAP3,
- PMUX_FUNC_DAP4,
- PMUX_FUNC_DAP5,
- PMUX_FUNC_DISPA,
- PMUX_FUNC_DISPB,
- PMUX_FUNC_EMC_TEST0_DLL,
- PMUX_FUNC_EMC_TEST1_DLL,
+ PMUX_FUNC_DAP,
+ PMUX_FUNC_DDR,
+ PMUX_FUNC_DEV3,
+ PMUX_FUNC_DISPLAYA,
+ PMUX_FUNC_DISPLAYB,
+ PMUX_FUNC_DTV,
+ PMUX_FUNC_EXTPERIPH1,
+ PMUX_FUNC_EXTPERIPH2,
+ PMUX_FUNC_EXTPERIPH3,
PMUX_FUNC_GMI,
- PMUX_FUNC_GMI_INT,
+ PMUX_FUNC_GMI_ALT,
+ PMUX_FUNC_HDA,
+ PMUX_FUNC_HDCP,
PMUX_FUNC_HDMI,
+ PMUX_FUNC_HSI,
PMUX_FUNC_I2C1,
PMUX_FUNC_I2C2,
PMUX_FUNC_I2C3,
- PMUX_FUNC_IDE,
+ PMUX_FUNC_I2C4,
+ PMUX_FUNC_I2CPWR,
+ PMUX_FUNC_I2S0,
+ PMUX_FUNC_I2S1,
+ PMUX_FUNC_I2S2,
+ PMUX_FUNC_I2S3,
+ PMUX_FUNC_I2S4,
+ PMUX_FUNC_INVALID,
PMUX_FUNC_KBC,
PMUX_FUNC_MIO,
- PMUX_FUNC_MIPI_HS,
PMUX_FUNC_NAND,
- PMUX_FUNC_OSC,
+ PMUX_FUNC_NAND_ALT,
PMUX_FUNC_OWR,
PMUX_FUNC_PCIE,
- PMUX_FUNC_PLLA_OUT,
- PMUX_FUNC_PLLC_OUT1,
- PMUX_FUNC_PLLM_OUT1,
- PMUX_FUNC_PLLP_OUT2,
- PMUX_FUNC_PLLP_OUT3,
- PMUX_FUNC_PLLP_OUT4,
- PMUX_FUNC_PWM,
- PMUX_FUNC_PWR_INTR,
- PMUX_FUNC_PWR_ON,
+ PMUX_FUNC_PWM0,
+ PMUX_FUNC_PWM1,
+ PMUX_FUNC_PWM2,
+ PMUX_FUNC_PWM3,
+ PMUX_FUNC_PWR_INT_N,
PMUX_FUNC_RTCK,
+ PMUX_FUNC_SATA,
PMUX_FUNC_SDMMC1,
PMUX_FUNC_SDMMC2,
PMUX_FUNC_SDMMC3,
PMUX_FUNC_SDMMC4,
- PMUX_FUNC_SFLASH,
PMUX_FUNC_SPDIF,
PMUX_FUNC_SPI1,
PMUX_FUNC_SPI2,
PMUX_FUNC_SPI2_ALT,
PMUX_FUNC_SPI3,
PMUX_FUNC_SPI4,
+ PMUX_FUNC_SPI5,
+ PMUX_FUNC_SPI6,
+ PMUX_FUNC_SYSCLK,
+ PMUX_FUNC_TEST,
PMUX_FUNC_TRACE,
- PMUX_FUNC_TWC,
PMUX_FUNC_UARTA,
PMUX_FUNC_UARTB,
PMUX_FUNC_UARTC,
PMUX_FUNC_UARTD,
PMUX_FUNC_UARTE,
PMUX_FUNC_ULPI,
- PMUX_FUNC_VI,
- PMUX_FUNC_VI_SENSOR_CLK,
- PMUX_FUNC_XIO,
- PMUX_FUNC_BLINK,
- PMUX_FUNC_CEC,
- PMUX_FUNC_CLK12,
- PMUX_FUNC_DAP,
- PMUX_FUNC_DAPSDMMC2,
- PMUX_FUNC_DDR,
- PMUX_FUNC_DEV3,
- PMUX_FUNC_DTV,
- PMUX_FUNC_VI_ALT1,
- PMUX_FUNC_VI_ALT2,
- PMUX_FUNC_VI_ALT3,
- PMUX_FUNC_EMC_DLL,
- PMUX_FUNC_EXTPERIPH1,
- PMUX_FUNC_EXTPERIPH2,
- PMUX_FUNC_EXTPERIPH3,
- PMUX_FUNC_GMI_ALT,
- PMUX_FUNC_HDA,
- PMUX_FUNC_HSI,
- PMUX_FUNC_I2C4,
- PMUX_FUNC_I2C5,
- PMUX_FUNC_I2CPWR,
- PMUX_FUNC_I2S0,
- PMUX_FUNC_I2S1,
- PMUX_FUNC_I2S2,
- PMUX_FUNC_I2S3,
- PMUX_FUNC_I2S4,
- PMUX_FUNC_NAND_ALT,
- PMUX_FUNC_POPSDIO4,
- PMUX_FUNC_POPSDMMC4,
- PMUX_FUNC_PWM0,
- PMUX_FUNC_PWM1,
- PMUX_FUNC_PWM2,
- PMUX_FUNC_PWM3,
- PMUX_FUNC_SATA,
- PMUX_FUNC_SPI5,
- PMUX_FUNC_SPI6,
- PMUX_FUNC_SYSCLK,
PMUX_FUNC_VGP1,
PMUX_FUNC_VGP2,
PMUX_FUNC_VGP3,
PMUX_FUNC_VGP4,
PMUX_FUNC_VGP5,
PMUX_FUNC_VGP6,
- PMUX_FUNC_CLK_12M_OUT,
- PMUX_FUNC_HDCP,
- PMUX_FUNC_TEST,
- PMUX_FUNC_CORE_PWR_REQ,
- PMUX_FUNC_CPU_PWR_REQ,
- PMUX_FUNC_PWR_INT_N,
- PMUX_FUNC_CLK_32K_IN,
- PMUX_FUNC_SAFE,
-
- PMUX_FUNC_MAX,
-
- PMUX_FUNC_RSVD1 = 0x8000,
- PMUX_FUNC_RSVD2 = 0x8001,
- PMUX_FUNC_RSVD3 = 0x8002,
- PMUX_FUNC_RSVD4 = 0x8003,
-};
-
-/* return 1 if a pmux_func is in range */
-#define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
- || (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
-
-/* return 1 if a pingrp is in range */
-#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
-
-/* The pullup/pulldown state of a pin group */
-enum pmux_pull {
- PMUX_PULL_NORMAL = 0,
- PMUX_PULL_DOWN,
- PMUX_PULL_UP,
-};
-/* return 1 if a pin_pupd_is in range */
-#define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
- ((pupd) <= PMUX_PULL_UP))
-
-/* Defines whether a pin group is tristated or in normal operation */
-enum pmux_tristate {
- PMUX_TRI_NORMAL = 0,
- PMUX_TRI_TRISTATE = 1,
-};
-/* return 1 if a pin_tristate_is in range */
-#define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
- && ((tristate) <= PMUX_TRI_TRISTATE))
-
-enum pmux_pin_io {
- PMUX_PIN_OUTPUT = 0,
- PMUX_PIN_INPUT = 1,
-};
-/* return 1 if a pin_io_is in range */
-#define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
- ((io) <= PMUX_PIN_INPUT))
-
-enum pmux_pin_lock {
- PMUX_PIN_LOCK_DEFAULT = 0,
- PMUX_PIN_LOCK_DISABLE,
- PMUX_PIN_LOCK_ENABLE,
-};
-/* return 1 if a pin_lock is in range */
-#define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
- ((lock) <= PMUX_PIN_LOCK_ENABLE))
-
-enum pmux_pin_od {
- PMUX_PIN_OD_DEFAULT = 0,
- PMUX_PIN_OD_DISABLE,
- PMUX_PIN_OD_ENABLE,
-};
-/* return 1 if a pin_od is in range */
-#define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
- ((od) <= PMUX_PIN_OD_ENABLE))
-
-enum pmux_pin_ioreset {
- PMUX_PIN_IO_RESET_DEFAULT = 0,
- PMUX_PIN_IO_RESET_DISABLE,
- PMUX_PIN_IO_RESET_ENABLE,
-};
-/* return 1 if a pin_ioreset_is in range */
-#define pmux_pin_ioreset_isvalid(ioreset) \
- (((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
- ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
-
-/* Available power domains used by pin groups */
-enum pmux_vddio {
- PMUX_VDDIO_BB = 0,
- PMUX_VDDIO_LCD,
- PMUX_VDDIO_VI,
- PMUX_VDDIO_UART,
- PMUX_VDDIO_DDR,
- PMUX_VDDIO_NAND,
- PMUX_VDDIO_SYS,
- PMUX_VDDIO_AUDIO,
- PMUX_VDDIO_SD,
- PMUX_VDDIO_CAM,
- PMUX_VDDIO_GMI,
- PMUX_VDDIO_PEXCTL,
- PMUX_VDDIO_SDMMC1,
- PMUX_VDDIO_SDMMC3,
- PMUX_VDDIO_SDMMC4,
-
- PMUX_VDDIO_NONE
-};
-
-#define PGRP_SLWF_NONE -1
-#define PGRP_SLWF_MAX 3
-#define PGRP_SLWR_NONE PGRP_SLWF_NONE
-#define PGRP_SLWR_MAX PGRP_SLWF_MAX
-
-#define PGRP_DRVUP_NONE -1
-#define PGRP_DRVUP_MAX 127
-#define PGRP_DRVDN_NONE PGRP_DRVUP_NONE
-#define PGRP_DRVDN_MAX PGRP_DRVUP_MAX
-
-/* return 1 if a padgrp is in range */
-#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
-
-/* return 1 if a slew-rate rising/falling edge value is in range */
-#define pmux_pad_slw_isvalid(slw) (((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX))
-
-/* return 1 if a driver output pull-up/down strength code value is in range */
-#define pmux_pad_drv_isvalid(drv) (((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX))
-
-/* return 1 if a low-power mode value is in range */
-#define pmux_pad_lpmd_isvalid(lpm) (((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X))
-
-/* Defines a pin group cfg's low-power mode select */
-enum pgrp_lpmd {
- PGRP_LPMD_X8 = 0,
- PGRP_LPMD_X4,
- PGRP_LPMD_X2,
- PGRP_LPMD_X,
- PGRP_LPMD_NONE = -1,
-};
-
-/* Defines whether a pin group cfg's schmidt is enabled or not */
-enum pgrp_schmt {
- PGRP_SCHMT_DISABLE = 0,
- PGRP_SCHMT_ENABLE = 1,
-};
-
-/* Defines whether a pin group cfg's high-speed mode is enabled or not */
-enum pgrp_hsm {
- PGRP_HSM_DISABLE = 0,
- PGRP_HSM_ENABLE = 1,
-};
-
-/*
- * This defines the configuration for a pin group's pad control config
- */
-struct padctrl_config {
- enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
- int slwf; /* falling edge slew */
- int slwr; /* rising edge slew */
- int drvup; /* pull-up drive strength */
- int drvdn; /* pull-down drive strength */
- enum pgrp_lpmd lpmd; /* low-power mode selection */
- enum pgrp_schmt schmt; /* schmidt enable */
- enum pgrp_hsm hsm; /* high-speed mode enable */
-};
-
-/* t30 pin drive group and pin mux registers */
-#define PDRIVE_PINGROUP_OFFSET (0x868 >> 2)
-#define PMUX_OFFSET ((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
- PDRIVE_PINGROUP_COUNT)
-struct pmux_tri_ctlr {
- uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
- uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */
- uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
- uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
- uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
- uint pmt_reserved4[4]; /* _TRI_STATE_REG_A/B/C/D in t20 */
- uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
-
- uint pmt_reserved[528]; /* ABP_MISC_PP_ reserved offs 28-864 */
-
- uint pmt_drive[PDRIVE_PINGROUP_COUNT]; /* pin drive grps offs 868 */
- uint pmt_reserved5[PMUX_OFFSET];
- uint pmt_ctl[PINGRP_COUNT]; /* mux/pupd/tri regs, offset 0x3000 */
-};
-
-/*
- * This defines the configuration for a pin, including the function assigned,
- * pull up/down settings and tristate settings. Having set up one of these
- * you can call pinmux_config_pingroup() to configure a pin in one step. Also
- * available is pinmux_config_table() to configure a list of pins.
- */
-struct pingroup_config {
- enum pmux_pingrp pingroup; /* pin group PINGRP_... */
- enum pmux_func func; /* function to assign FUNC_... */
- enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
- enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
- enum pmux_pin_io io; /* input or output PMUX_PIN_... */
- enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
- enum pmux_pin_od od; /* open-drain or push-pull driver */
- enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
+ PMUX_FUNC_VI,
+ PMUX_FUNC_VI_ALT1,
+ PMUX_FUNC_VI_ALT2,
+ PMUX_FUNC_VI_ALT3,
+ PMUX_FUNC_RSVD1,
+ PMUX_FUNC_RSVD2,
+ PMUX_FUNC_RSVD3,
+ PMUX_FUNC_RSVD4,
+ PMUX_FUNC_COUNT,
};
-/* Set a pin group to tristate */
-void pinmux_tristate_enable(enum pmux_pingrp pin);
-
-/* Set a pin group to normal (non tristate) */
-void pinmux_tristate_disable(enum pmux_pingrp pin);
-
-/* Set the pull up/down feature for a pin group */
-void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
-
-/* Set the mux function for a pin group */
-void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
-
-/* Set the complete configuration for a pin group */
-void pinmux_config_pingroup(struct pingroup_config *config);
-
-/* Set a pin group to tristate or normal */
-void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
-
-/* Set a pin group as input or output */
-void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
-
-/**
- * Configure a list of pin groups
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void pinmux_config_table(struct pingroup_config *config, int len);
-
-/* Set a group of pins from a table */
-void pinmux_init(void);
-
-/**
- * Set the GP pad configs
- *
- * @param config List of config items
- * @param len Number of config items in list
- */
-void padgrp_config_table(struct padctrl_config *config, int len);
+#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
+#define TEGRA_PMX_HAS_DRVGRPS
+#include <asm/arch-tegra/pinmux.h>
-#endif /* _TEGRA30_PINMUX_H_ */
+#endif /* _TEGRA30_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra30/usb.h b/arch/arm/include/asm/arch-tegra30/usb.h
deleted file mode 100644
index ab9b760..0000000
--- a/arch/arm/include/asm/arch-tegra30/usb.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2013 NVIDIA Corporation
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _TEGRA30_USB_H_
-#define _TEGRA30_USB_H_
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
- /* 0x000 */
- uint id;
- uint reserved0;
- uint host;
- uint device;
-
- /* 0x010 */
- uint txbuf;
- uint rxbuf;
- uint reserved1[2];
-
- /* 0x020 */
- uint reserved2[56];
-
- /* 0x100 */
- u16 cap_length;
- u16 hci_version;
- uint hcs_params;
- uint hcc_params;
- uint reserved3[5];
-
- /* 0x120 */
- uint dci_version;
- uint dcc_params;
- uint reserved4[2];
-
- /* 0x130 */
- uint usb_cmd;
- uint usb_sts;
- uint usb_intr;
- uint frindex;
-
- /* 0x140 */
- uint reserved5;
- uint periodic_list_base;
- uint async_list_addr;
- uint reserved5_1;
-
- /* 0x150 */
- uint burst_size;
- uint tx_fill_tuning;
- uint reserved6;
- uint icusb_ctrl;
-
- /* 0x160 */
- uint ulpi_viewport;
- uint reserved7[3];
-
- /* 0x170 */
- uint reserved;
- uint port_sc1;
- uint reserved8[6];
-
- /* 0x190 */
- uint reserved9[8];
-
- /* 0x1b0 */
- uint reserved10;
- uint hostpc1_devlc;
- uint reserved10_1[2];
-
- /* 0x1c0 */
- uint reserved10_2[4];
-
- /* 0x1d0 */
- uint reserved10_3[4];
-
- /* 0x1e0 */
- uint reserved10_4[4];
-
- /* 0x1f0 */
- uint reserved10_5;
- uint otgsc;
- uint usb_mode;
- uint reserved10_6;
-
- /* 0x200 */
- uint endpt_nak;
- uint endpt_nak_enable;
- uint endpt_setup_stat;
- uint reserved11_1[0x7D];
-
- /* 0x400 */
- uint susp_ctrl;
- uint phy_vbus_sensors;
- uint phy_vbus_wakeup_id;
- uint phy_alt_vbus_sys;
-
- /* 0x410 */
- uint usb1_legacy_ctrl;
- uint reserved12[3];
-
- /* 0x420 */
- uint reserved13[56];
-
- /* 0x500 */
- uint reserved14[64 * 3];
-
- /* 0x800 */
- uint utmip_pll_cfg0;
- uint utmip_pll_cfg1;
- uint utmip_xcvr_cfg0;
- uint utmip_bias_cfg0;
-
- /* 0x810 */
- uint utmip_hsrx_cfg0;
- uint utmip_hsrx_cfg1;
- uint utmip_fslsrx_cfg0;
- uint utmip_fslsrx_cfg1;
-
- /* 0x820 */
- uint utmip_tx_cfg0;
- uint utmip_misc_cfg0;
- uint utmip_misc_cfg1;
- uint utmip_debounce_cfg0;
-
- /* 0x830 */
- uint utmip_bat_chrg_cfg0;
- uint utmip_spare_cfg0;
- uint utmip_xcvr_cfg1;
- uint utmip_bias_cfg1;
-};
-
-/* USB2_IF_ULPI_TIMING_CTRL_0 */
-#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
-#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
-
-/* USB2_IF_ULPI_TIMING_CTRL_1 */
-#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
-#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
-#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
-#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
-#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
-#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
-
-/* USB2D_HOSTPC1_DEVLC_0 */
-#define PTS_SHIFT 29
-#define PTS_MASK (0x7U << PTS_SHIFT)
-
-#define STS (1 << 28)
-#endif /* _TEGRA30_USB_H_ */
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 04925bc..729723a 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -574,6 +574,8 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
u32 txdone, u32 txdone_mask, u32 opp);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
+void usb_fake_mac_from_die_id(u32 *id);
+
/* HW Init Context */
#define OMAP_INIT_CONTEXT_SPL 0
#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1