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author | Tom Rini <trini@ti.com> | 2014-10-07 07:38:39 -0400 |
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committer | Tom Rini <trini@ti.com> | 2014-10-07 07:38:39 -0400 |
commit | dd0204e48d05f41480743a798b94d5484b664639 (patch) | |
tree | 0dada741b0dc5b60dcc63ae0dfe783b6935e7eba /arch/arm/include/asm/arch-uniphier/arm-mpcore.h | |
parent | 742de9076e8a8f44b77794b43e6175d86b897996 (diff) | |
parent | c19a8bc5711ec63e905ef91f045a1489f0aa3cb0 (diff) | |
download | u-boot-imx-dd0204e48d05f41480743a798b94d5484b664639.zip u-boot-imx-dd0204e48d05f41480743a798b94d5484b664639.tar.gz u-boot-imx-dd0204e48d05f41480743a798b94d5484b664639.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/include/asm/arch-uniphier/arm-mpcore.h')
-rw-r--r-- | arch/arm/include/asm/arch-uniphier/arm-mpcore.h | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-uniphier/arm-mpcore.h b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h new file mode 100644 index 0000000..cf7cd46 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/arm-mpcore.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2011-2014 Panasonic Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_ARM_MPCORE_H +#define ARCH_ARM_MPCORE_H + +/* Snoop Control Unit */ +#define SCU_OFFSET 0x00 + +/* SCU Control Register */ +#define SCU_CTRL 0x00 +/* SCU Configuration Register */ +#define SCU_CONF 0x04 +/* SCU CPU Power Status Register */ +#define SCU_PWR_STATUS 0x08 +/* SCU Invalidate All Registers in Secure State */ +#define SCU_INV_ALL 0x0C +/* SCU Filtering Start Address Register */ +#define SCU_FILTER_START 0x40 +/* SCU Filtering End Address Register */ +#define SCU_FILTER_END 0x44 +/* SCU Access Control Register */ +#define SCU_SAC 0x50 +/* SCU Non-secure Access Control Register */ +#define SCU_SNSAC 0x54 + +/* Global Timer */ +#define GLOBAL_TIMER_OFFSET 0x200 + +/* Global Timer Counter Registers */ +#define GTIMER_CNT_L 0x00 +#define GTIMER_CNT_H 0x04 +/* Global Timer Control Register */ +#define GTIMER_CTRL 0x08 +/* Global Timer Interrupt Status Register */ +#define GTIMER_STAT 0x0C +/* Comparator Value Registers */ +#define GTIMER_CMP_L 0x10 +#define GTIMER_CMP_H 0x14 +/* Auto-increment Register */ +#define GTIMER_INC 0x18 + +#endif /* ARCH_ARM_MPCORE_H */ |