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| author | Stephen Warren <swarren@nvidia.com> | 2014-06-25 10:57:27 -0600 |
|---|---|---|
| committer | Heiko Schocher <hs@denx.de> | 2014-07-03 06:29:19 +0200 |
| commit | 68049a082b8aedf09e769e61885e000e598bb516 (patch) | |
| tree | 26780e2fead018bee3b9e1d9a9f25f41e47d401a /arch/arm/include/asm/arch-tegra | |
| parent | fe8b3212b7938861eacdefe6115810303a96f9cc (diff) | |
| download | u-boot-imx-68049a082b8aedf09e769e61885e000e598bb516.zip u-boot-imx-68049a082b8aedf09e769e61885e000e598bb516.tar.gz u-boot-imx-68049a082b8aedf09e769e61885e000e598bb516.tar.bz2 | |
i2c: tegra: use repeated start for reads
I2C read transactions are typically implemented as follows:
START(write) address REPEATED_START(read) data... STOP
However, Tegra's I2C driver currently implements reads as follows:
START(write) address STOP START(read) data... STOP
This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Yen Lin <yelin@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra/tegra_i2c.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra/tegra_i2c.h b/arch/arm/include/asm/arch-tegra/tegra_i2c.h index 853e59b..7ca6907 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_i2c.h +++ b/arch/arm/include/asm/arch-tegra/tegra_i2c.h @@ -124,6 +124,8 @@ struct i2c_ctlr { /* bit fields definitions for IO Packet Header 3 format */ #define PKT_HDR3_READ_MODE_SHIFT 19 #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_REPEAT_START_SHIFT 16 +#define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT) #define PKT_HDR3_SLAVE_ADDR_SHIFT 0 #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) |