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| author | Allen Martin <amartin@nvidia.com> | 2013-03-16 18:58:05 +0000 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2013-03-25 09:56:05 -0700 |
| commit | 7a49ba6e5b81713c5c8f8275a7ecd1036ca583d4 (patch) | |
| tree | 38c116de21921270d92c7444d85676e2994569e0 /arch/arm/include/asm/arch-tegra20/tegra20_sflash.h | |
| parent | 2a3c5bc29c621faf2f830c464cc395b3174800f1 (diff) | |
| download | u-boot-imx-7a49ba6e5b81713c5c8f8275a7ecd1036ca583d4.zip u-boot-imx-7a49ba6e5b81713c5c8f8275a7ecd1036ca583d4.tar.gz u-boot-imx-7a49ba6e5b81713c5c8f8275a7ecd1036ca583d4.tar.bz2 | |
tegra: spi: pull register structs out of headers
Move register structs from headers into .c files and use common name.
This is in preparation of making common fdt front end for SPI
drivers.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra20/tegra20_sflash.h')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra20/tegra20_sflash.h | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h index 26a8402..28775db 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h +++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h @@ -27,49 +27,4 @@ #include <asm/types.h> -struct spi_tegra { - u32 command; /* SPI_COMMAND_0 register */ - u32 status; /* SPI_STATUS_0 register */ - u32 rx_cmp; /* SPI_RX_CMP_0 register */ - u32 dma_ctl; /* SPI_DMA_CTL_0 register */ - u32 tx_fifo; /* SPI_TX_FIFO_0 register */ - u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ - u32 rx_fifo; /* SPI_RX_FIFO_0 register */ -}; - -#define SPI_CMD_GO (1 << 30) -#define SPI_CMD_ACTIVE_SCLK_SHIFT 26 -#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) -#define SPI_CMD_CK_SDA (1 << 21) -#define SPI_CMD_ACTIVE_SDA_SHIFT 18 -#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) -#define SPI_CMD_CS_POL (1 << 16) -#define SPI_CMD_TXEN (1 << 15) -#define SPI_CMD_RXEN (1 << 14) -#define SPI_CMD_CS_VAL (1 << 13) -#define SPI_CMD_CS_SOFT (1 << 12) -#define SPI_CMD_CS_DELAY (1 << 9) -#define SPI_CMD_CS3_EN (1 << 8) -#define SPI_CMD_CS2_EN (1 << 7) -#define SPI_CMD_CS1_EN (1 << 6) -#define SPI_CMD_CS0_EN (1 << 5) -#define SPI_CMD_BIT_LENGTH (1 << 4) -#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F - -#define SPI_STAT_BSY (1 << 31) -#define SPI_STAT_RDY (1 << 30) -#define SPI_STAT_RXF_FLUSH (1 << 29) -#define SPI_STAT_TXF_FLUSH (1 << 28) -#define SPI_STAT_RXF_UNR (1 << 27) -#define SPI_STAT_TXF_OVF (1 << 26) -#define SPI_STAT_RXF_EMPTY (1 << 25) -#define SPI_STAT_RXF_FULL (1 << 24) -#define SPI_STAT_TXF_EMPTY (1 << 23) -#define SPI_STAT_TXF_FULL (1 << 22) -#define SPI_STAT_SEL_TXRX_N (1 << 16) -#define SPI_STAT_CUR_BLKCNT (1 << 15) - -#define SPI_TIMEOUT 1000 -#define TEGRA_SPI_MAX_FREQ 52000000 - #endif /* _TEGRA20_SPI_H_ */ |