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author | Stephen Warren <swarren@nvidia.com> | 2014-03-21 12:28:53 -0600 |
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committer | Tom Warren <twarren@nvidia.com> | 2014-04-17 08:41:05 -0700 |
commit | 19ed7b4ecf6bdcf991d0a63aac3faa80b6df43cb (patch) | |
tree | b5d9181495ded2c5d57752c2a96abdd5b404452a /arch/arm/include/asm/arch-tegra20/apb_misc.h | |
parent | 07bbd48b4785f28b41ceeab4337d7690837e6ec1 (diff) | |
download | u-boot-imx-19ed7b4ecf6bdcf991d0a63aac3faa80b6df43cb.zip u-boot-imx-19ed7b4ecf6bdcf991d0a63aac3faa80b6df43cb.tar.gz u-boot-imx-19ed7b4ecf6bdcf991d0a63aac3faa80b6df43cb.tar.bz2 |
ARM: tegra: use apb_misc.h in more places
Tegra's "APB misc" register region contains various miscellaneous
registers and the Tegra pinmux registers. Some code that touches the
misc registers currently uses struct pmux_tri_ctlr, which is intended to
be a definition of pinmux registers, rather than struct apb_misc_pp_ctrl,
which is intended to be a definition of the miscellaneous registers.
Convert all such code to use struct apb_misc_pp_ctrl, since struct
pmux_tri_ctlr goes away in the next patch.
This requires adding a missing field definition to struct
apb_misc_pp_ctrl, and moving the header into a more common location.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra20/apb_misc.h')
-rw-r--r-- | arch/arm/include/asm/arch-tegra20/apb_misc.h | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/arch/arm/include/asm/arch-tegra20/apb_misc.h b/arch/arm/include/asm/arch-tegra20/apb_misc.h deleted file mode 100644 index f314f5a..0000000 --- a/arch/arm/include/asm/arch-tegra20/apb_misc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2012 The Chromium OS Authors. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _GP_PADCTRL_H_ -#define _GP_PADCTRL_H_ - -/* APB_MISC_PP registers */ -struct apb_misc_pp_ctlr { - u32 reserved0[2]; - u32 strapping_opt_a;/* 0x08: APB_MISC_PP_STRAPPING_OPT_A */ -}; - -/* bit fields definitions for APB_MISC_PP_STRAPPING_OPT_A register */ -#define RAM_CODE_SHIFT 4 -#define RAM_CODE_MASK (0xf << RAM_CODE_SHIFT) - -#endif |