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author | Wolfgang Denk <wd@denx.de> | 2012-05-20 21:31:26 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2012-05-20 21:31:26 +0200 |
commit | ee3a55fdf00b54391e406217e53674449e70d78b (patch) | |
tree | 0c7edb3ba668e5a215c42e8b1429cc3f394351b2 /arch/arm/include/asm/arch-tegra2/sdram_param.h | |
parent | 6bc337fb13003a9a949dfb2713e308fb97faae8a (diff) | |
parent | 2ca4a209a5b961ad1be8782c68dabe326d77dfaf (diff) | |
download | u-boot-imx-ee3a55fdf00b54391e406217e53674449e70d78b.zip u-boot-imx-ee3a55fdf00b54391e406217e53674449e70d78b.tar.gz u-boot-imx-ee3a55fdf00b54391e406217e53674449e70d78b.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
omap4: do not enable auxiliary cores
omap4: do not enable fs-usb module
omap4: panda: disable uart2 pads during boot
igep00x0: change mpurate from 500 to auto
igep00x0: enable the use of a plain text file
tegra2: trivially enable 13 mhz crystal frequency
tegra: Enable keyboard for Seaboard
tegra: Switch on console mux and use environment for console
tegra: Add tegra keyboard driver
tegra: fdt: Add keyboard definitions for Seaboard
tegra: fdt: Add keyboard controller definition
tegra: Add keyboard support to funcmux
input: Add support for keyboard matrix decoding from an fdt
input: Add generic keyboard input handler
input: Add linux/input.h for key code support
fdt: Add fdtdec functions to read byte array
tegra: Enable LP0 on Seaboard
tegra: fdt: Add EMC data for Tegra2 Seaboard
tegra: i2c: Add function to find DVC bus
fdt: tegra: Add EMC node to device tree
tegra: Add EMC settings for Seaboard
tegra: Turn off power detect in board init
tegra: Set up warmboot code on Nvidia boards
tegra: Setup PMC scratch info from ap20 setup
tegra: Add warmboot implementation
tegra: Set up PMU for Nvidia boards
tegra: Add PMU to manage power supplies
tegra: Add EMC support for optimal memory timings
tegra: Add header file for APB_MISC register
tegra: Add tegra_get_chip_type() to detect SKU
tegra: Add flow, gp_padctl, fuse, sdram headers
tegra: Add crypto library for warmboot code
tegra: Add functions to access low-level Osc/PLL details
tegra: Move ap20.h header into arch location
Add AES crypto library
i2c: Add TPS6586X driver
Add abs() macro to return absolute value
fdt: Add function to return next compatible subnode
fdt: Add function to locate an array in the device tree
i.MX28: Avoid redefining serial_put[cs]()
i.MX28: Check if WP detection is implemented at all
i.MX28: Add battery boot components to SPL
i.MX28: Reorder battery status functions in SPL
i.MX28: Add LRADC init to i.MX28 SPL
i.MX28: Add LRADC register definitions
i.MX28: Shut down the LCD controller before reset
i.MX28: Add LCDIF register definitions
i.MX28: Implement boot pads sampling and reporting
i.MX28: Improve passing of data from SPL to U-Boot
M28EVK: Add SD update command
M28EVK: Implement support for new board V2.0
FEC: Abstract out register setup
MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
i.MX28: Add delay after CPU bypass is cleared
spi: mxs: Allow other chip selects to work
spi: mxs: Introduce spi_cs_is_valid()
mx53loco: Remove unneeded gpio_set_value()
mx53loco: Add CONFIG_REVISION_TAG
mx53loco: Turn on VUSB regulator
mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
pmic: dialog: Avoid name conflicts
imx: Add u-boot.imx as target for ARM9 i.MX SOCs
i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
imx: usb: There is no such register
i.MX25: usb: Set PORTSCx register
imx: nand: Support flash based BBT
i.MX25: This architecture has a GPIO4 too
i.MX25: esdhc: Add mxc_get_clock infrastructure
i.MX6: mx6q_sabrelite: add SATA bindings
i.MX6: add enable_sata_clock()
i.MX6: Add ANATOP regulator init
mx28evk: add NAND support
USB: ehci-mx6: Fix broken IO access
M28: Scan only first 512 MB of DRAM to avoid memory wraparound
Revert "i.MX28: Enable additional DRAM address bits"
M28: Enable FDT support
mx53loco: Add support for 1GHz operation for DA9053-based boards
mx53loco: Allow to print CPU information at a later stage
mx5: Add clock config interface
imx-common: Factor out get_ahb_clk()
i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
mx31pdk: Allow booting a zImage kernel
mx6qarm2: Allow booting a zImage kernel
mx6qsabrelite: Allow booting a zImage kernel
mx28evk: Allow booting a zImage kernel
m28evk: Allow to booting a dt kernel
mx28evk: Allow to booting a dt kernel
mx6qsabrelite: No need to set the direction for GPIO3_23 again
pmic: Add support for the Dialog DA9053 PMIC
MX53: mx53loco: Add SATA support
MX53: Add support to ESG ima3 board
SATA: add driver for MX5 / MX6 SOCs
MX53: add function to set SATA clock to internal
SATA: check for return value from sata functions
MX5: Add definitions for SATA controller
NET: fec_mxc.c: Add a way to disable auto negotiation
Define UART4 and UART5 base addresses
EXYNOS: Change bits per pixel value proper for u-boot.
EXYNOS: support TRATS board display function
LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
EXYNOS: support EXYNOS MIPI DSI interface driver.
EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
LCD: add data structure for EXYNOS display driver
EXYNOS: add LCD and MIPI DSI clock interface.
EXYNOS: definitions of system resgister and power management registers.
SMDK5250: fix compiler warning
misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
misc:pmic:max8997 MAX8997 support for PMIC driver
TRATS: modify the trats's configuration
ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
cm-t35: add I2C multi-bus support
include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
omap3: Introduce weak misc_init_r
omap730p2: Remove empty misc_init_r
omap5912osk: Remove empty misc_init_r
omap4+: Remove CONFIG_ARCH_CPU_INIT
omap4: Remove CONFIG_SYS_MMC_SET_DEV
OMAP3: pandora: drop console kernel argument
OMAP3: pandora: revise GPIO configuration
...
Diffstat (limited to 'arch/arm/include/asm/arch-tegra2/sdram_param.h')
-rw-r--r-- | arch/arm/include/asm/arch-tegra2/sdram_param.h | 148 |
1 files changed, 148 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra2/sdram_param.h b/arch/arm/include/asm/arch-tegra2/sdram_param.h new file mode 100644 index 0000000..6c427d0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/sdram_param.h @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2010, 2011 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SDRAM_PARAM_H_ +#define _SDRAM_PARAM_H_ + +/* + * Defines the number of 32-bit words provided in each set of SDRAM parameters + * for arbitration configuration data. + */ +#define BCT_SDRAM_ARB_CONFIG_WORDS 27 + +enum memory_type { + MEMORY_TYPE_NONE = 0, + MEMORY_TYPE_DDR, + MEMORY_TYPE_LPDDR, + MEMORY_TYPE_DDR2, + MEMORY_TYPE_LPDDR2, + MEMORY_TYPE_NUM, + MEMORY_TYPE_FORCE32 = 0x7FFFFFFF +}; + +/* Defines the SDRAM parameter structure */ +struct sdram_params { + enum memory_type memory_type; + u32 pllm_charge_pump_setup_control; + u32 pllm_loop_filter_setup_control; + u32 pllm_input_divider; + u32 pllm_feedback_divider; + u32 pllm_post_divider; + u32 pllm_stable_time; + u32 emc_clock_divider; + u32 emc_auto_cal_interval; + u32 emc_auto_cal_config; + u32 emc_auto_cal_wait; + u32 emc_pin_program_wait; + u32 emc_rc; + u32 emc_rfc; + u32 emc_ras; + u32 emc_rp; + u32 emc_r2w; + u32 emc_w2r; + u32 emc_r2p; + u32 emc_w2p; + u32 emc_rd_rcd; + u32 emc_wr_rcd; + u32 emc_rrd; + u32 emc_rext; + u32 emc_wdv; + u32 emc_quse; + u32 emc_qrst; + u32 emc_qsafe; + u32 emc_rdv; + u32 emc_refresh; + u32 emc_burst_refresh_num; + u32 emc_pdex2wr; + u32 emc_pdex2rd; + u32 emc_pchg2pden; + u32 emc_act2pden; + u32 emc_ar2pden; + u32 emc_rw2pden; + u32 emc_txsr; + u32 emc_tcke; + u32 emc_tfaw; + u32 emc_trpab; + u32 emc_tclkstable; + u32 emc_tclkstop; + u32 emc_trefbw; + u32 emc_quseextra; + u32 emc_fbioc_fg1; + u32 emc_fbio_dqsib_dly; + u32 emc_fbio_dqsib_dly_msb; + u32 emc_fbio_quse_dly; + u32 emc_fbio_quse_dly_msb; + u32 emc_fbio_cfg5; + u32 emc_fbio_cfg6; + u32 emc_fbio_spare; + u32 emc_mrs; + u32 emc_emrs; + u32 emc_mrw1; + u32 emc_mrw2; + u32 emc_mrw3; + u32 emc_mrw_reset_command; + u32 emc_mrw_reset_init_wait; + u32 emc_adr_cfg; + u32 emc_adr_cfg1; + u32 emc_emem_cfg; + u32 emc_low_latency_config; + u32 emc_cfg; + u32 emc_cfg2; + u32 emc_dbg; + u32 ahb_arbitration_xbar_ctrl; + u32 emc_cfg_dig_dll; + u32 emc_dll_xform_dqs; + u32 emc_dll_xform_quse; + u32 warm_boot_wait; + u32 emc_ctt_term_ctrl; + u32 emc_odt_write; + u32 emc_odt_read; + u32 emc_zcal_ref_cnt; + u32 emc_zcal_wait_cnt; + u32 emc_zcal_mrw_cmd; + u32 emc_mrs_reset_dll; + u32 emc_mrw_zq_init_dev0; + u32 emc_mrw_zq_init_dev1; + u32 emc_mrw_zq_init_wait; + u32 emc_mrs_reset_dll_wait; + u32 emc_emrs_emr2; + u32 emc_emrs_emr3; + u32 emc_emrs_ddr2_dll_enable; + u32 emc_mrs_ddr2_dll_reset; + u32 emc_emrs_ddr2_ocd_calib; + u32 emc_edr2_wait; + u32 emc_cfg_clktrim0; + u32 emc_cfg_clktrim1; + u32 emc_cfg_clktrim2; + u32 pmc_ddr_pwr; + u32 apb_misc_gp_xm2cfga_padctrl; + u32 apb_misc_gp_xm2cfgc_padctrl; + u32 apb_misc_gp_xm2cfgc_padctrl2; + u32 apb_misc_gp_xm2cfgd_padctrl; + u32 apb_misc_gp_xm2cfgd_padctrl2; + u32 apb_misc_gp_xm2clkcfg_padctrl; + u32 apb_misc_gp_xm2comp_padctrl; + u32 apb_misc_gp_xm2vttgen_padctrl; + u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; +}; +#endif |