Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: (145 commits)
  beagleboard: enable HUB power on all variants of the BeagleBoard
  dm3730: enable dpll5
  ehci-hcd: Allow cleanups to happen gracefully on a timeout.
  OMAP3: Add DSS driver for OMAP3
  led: Remove state-saving of led for toggle functionality and add toggle option to led command
  led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all'
  led: correct off/on locations in structure
  led: added cmd_led to Makefile
  BeagleBoard: fix LED 0/1 in driver
  Corrected LED name match finding avoiding extraneous Usage printouts
  BeagleBoard: config: updated default configuration
  BeagleBoard: config: Enabled multibus support for I2C in configuration
  BeagleBoard: config: add optargs/buddy/camera
  BeagleBoard: config: increase command-line functionality
  BeagleBoard: config: make mtest run
  BeagleBoard: config: enable DSS
  BeagleBoard: config: enable asix driver and dhcp
  BeagleBoard: config: enable networking
  BeagleBoard: config: decrease bootdelay to 2 seconds
  BeagleBoard: config: use uImage.beagle for tftp
  BeagleBoard: config: hardcode MAC for onboard SMSC
  BeagleBoard: config: load kernel from MMC ext, not FAT
  BeagleBoard: Configure DVI/S-video
  BeagleBoard: Added userbutton command
  BeagleBoard: turn off clocks in ehci_stop
  USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor
  beagleboard: add support for xM revision C
  beagle: pass expansionboard name in bootargs
  OMAP: Remove omapfb.debug=y from Beagle and Overo env settings
  OMAP3 Beagle Pin Mux initialization glitch fix
  da850: modifications for Logic PD Rev.3 AM18xx EVM
  da850: fix the channel number for EMAC teardown init
  da850: add support for Spectrum Digital AM18xx EVM
  da850: add support to wake up DSP during board init
  da850: modify the U-Boot prompt string
  da850: add NOR boot mode support
  da8xx: add support for multiple PLL controllers
  da850: indicate cache usage disable in config file
  dm365: modify boot prompt from dm365 to dm36x
  dm365: disable cache usage due to coherency issues
  dm6446: disable cache usage due to coherency issues
  OMAP3: Remove legacy mmc driver
  devkit8000: Use generic MMC driver
  TI OMAP3 SDP3430: Use generic MMC driver
  AM3517 CraneBoard: Use generic MMC driver
  OMAP3: pandora: Use generic MMC driver
  OMAP3: Zoom2: Use generic MMC driver
  OMAP3: Zoom1: Use generic MMC driver
  OMAP3: DIG297: Use generic MMC driver
  OMAP3: CM-T35: Use generic MMC driver
  am3517evm: Use generic MMC driver
  omap3evm: Use generic MMC driver
  omap3:clock: check cpu_family before enabling clks for IVA & CAM
  omap3:clock: configure GFX clock to 200MHz for AM/DM37x
  OMAP3/4: Increase console I/O buffer size
  PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE
  PXA: Fix CSB226, fix monitor length
  PXA: Fix Lubbock, remove redundant parenthesis
  armv7: cache: remove flush on un-aligned invalidate
  armv7: stronger barrier for cache-maintenance operations
  omap: enable caches at system start-up
  arm: do not force d-cache enable on all boards
  ORIGEN: Add MMC SPL support
  ARMV7: Add support for Samsung ORIGEN board
  i2c:gpio:s5p: Enable I2C GPIO on the GONI target
  i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)
  Tegra2: Use clock and pinmux functions to simplify code
  Tegra2: Add additional pin multiplexing features
  Tegra2: Add more clock support
  Tegra2: Add microsecond timer function
  ARM: remove broken "at91rm9200dk" board
  ARM: remove broken "m501sk" board
  ARM: remove broken "kb9202" board
  ARM: remove broken "csb637" board
  ARM: remove broken "cmc_pu2" board
  ARM: remove broken "at91cap9adk" board
  ARM: remove broken "voiceblue" board
  ARM: remove broken "smdk2400" board
  ARM: remove broken "sbc2410x" board
  ARM: remove broken "netstar" board
  ARM: remove broken "mx1fs2" board
  ARM: remove broken "lpd7a40x" boards
  ARM: remove broken "edb93xx" boards
  ARM: remove broken "B2" board
  ARM: remove broken "armadillo" board
  ARM: remove broken "assabet" board
  ARM: versatile: drop warnings
  IMX: scb9328: drop warnings
  MX31: imx31_litekit: make use of GPIO framework
  MX31: mx31ads: make use of GPIO framework
  MX5: mx51evk: make use of GPIO framework
  MX35: mx35pdk: make use of GPIO framework
  MX5: mx53loco: make use of GPIO framework
  MX5: mx53evk: make use of GPIO framework
  MX5: vision2: make use of GPIO framework
  MX5: mx53smd: make use of GPIO framework
  MX5: mx53ard: make use of GPIO framework
  MX25: zmx25: make use of GPIO framework
  MX5: efikamx: make use of GPIO framework
  MX31: QONG: make use of GPIO framework
  MX35: make use of GPIO framework for MX35 processor
  MX5: make use of GPIO framework for MX5 processor
  MX31: make use of GPIO framework for MX31 processor
  MX25: make use of GPIO framework for MX25 processor
  IMX: uniform GPIO interface using GPIO framework
  MX: MX35 / MX5: uniform clock command with powerpc
  MX35: MX35PDK: support additional RAM on CSD1
  mx53: ddr3: Update DD3 initialization
  ARM: MX51: PLL errata workaround
  ARM: versatilepb : drop warnings due to double definitions
  omap4: increase SRAM budget to fix build error
  omap4: fix build warning due to signed unsigned comparison
  mkimage: Fix 'Unknown OMAP image type - 5'
  omap: fix gpio related build breaks
  gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal)
  SMDKV310: MMC SPL: Remove unwanted dummy functions
  SMDKV310: Fix undefined reference error
  SMDKV310: Fix build error for smdkv310 board
  gpio:samsung s5p_ suffix add for GPIO functions
  mmc: S5P: Support DMA restarts at buffer boundaries
  SMDKV310: Fix host compilation of mkv310_image
  arm: fix bd pointer dereference prior initialization
  arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize
  mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF
  MX31: removed warnings due to clock.h
  integrator: convert to new build system
  integratorcp: make the board compile
  integratorap: remove hardcoded 32MB memory cmdline
  ...

1 files changed, 52 insertions, 75 deletions

diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
index 36e27b5..bd9d9ad 100644
--- a/arch/arm/include/asm/arch-tegra2/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -24,15 +24,34 @@
 #ifndef _CLK_RST_H_
 #define _CLK_RST_H_
 
+/* PLL registers - there are several PLLs in the clock controller */
+struct clk_pll {
+	uint pll_base;		/* the control register */
+	uint pll_out;		/* output control */
+	uint reserved;
+	uint pll_misc;		/* other misc things */
+};
+
+/* PLL registers - there are several PLLs in the clock controller */
+struct clk_pll_simple {
+	uint pll_base;		/* the control register */
+	uint pll_misc;		/* other misc things */
+};
+
+/*
+ * Most PLLs use the clk_pll structure, but some have a simpler two-member
+ * structure for which we use clk_pll_simple. The reason for this non-
+ * othogonal setup is not stated.
+ */
+#define TEGRA_CLK_PLLS		6
+#define TEGRA_CLK_SIMPLE_PLLS	3	/* Number of simple PLLs */
+#define TEGRA_CLK_REGS		3	/* Number of clock enable registers */
+
 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
 struct clk_rst_ctlr {
-	uint crc_rst_src;		/* _RST_SOURCE_0,	0x00 */
-	uint crc_rst_dev_l;		/* _RST_DEVICES_L_0,	0x04 */
-	uint crc_rst_dev_h;		/* _RST_DEVICES_H_0,	0x08 */
-	uint crc_rst_dev_u;		/* _RST_DEVICES_U_0,	0x0C */
-	uint crc_clk_out_enb_l;		/* _CLK_OUT_ENB_L_0,	0x10 */
-	uint crc_clk_out_enb_h;		/* _CLK_OUT_ENB_H_0,	0x14 */
-	uint crc_clk_out_enb_u;		/* _CLK_OUT_ENB_U_0,	0x18 */
+	uint crc_rst_src;			/* _RST_SOURCE_0,0x00 */
+	uint crc_rst_dev[TEGRA_CLK_REGS];	/* _RST_DEVICES_L/H/U_0 */
+	uint crc_clk_out_enb[TEGRA_CLK_REGS];	/* _CLK_OUT_ENB_L/H/U_0 */
 	uint crc_reserved0;		/* reserved_0,		0x1C */
 	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0,0x20 */
 	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
@@ -52,44 +71,11 @@ struct clk_rst_ctlr {
 	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
 	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
 
-	uint crc_pllc_base;		/* _PLLC_BASE_0,	0x80 */
-	uint crc_pllc_out;		/* _PLLC_OUT_0,		0x84 */
-	uint crc_reserved3;		/* reserved_3,		0x88 */
-	uint crc_pllc_misc;		/* _PLLC_MISC_0,	0x8C */
-
-	uint crc_pllm_base;		/* _PLLM_BASE_0,	0x90 */
-	uint crc_pllm_out;		/* _PLLM_OUT_0,		0x94 */
-	uint crc_reserved4;		/* reserved_4,		0x98 */
-	uint crc_pllm_misc;		/* _PLLM_MISC_0,	0x9C */
+	struct clk_pll crc_pll[TEGRA_CLK_PLLS];	/* PLLs from 0x80 to 0xdc */
 
-	uint crc_pllp_base;		/* _PLLP_BASE_0,	0xA0 */
-	uint crc_pllp_outa;		/* _PLLP_OUTA_0,	0xA4 */
-	uint crc_pllp_outb;		/* _PLLP_OUTB_0,	0xA8 */
-	uint crc_pllp_misc;		/* _PLLP_MISC_0,	0xAC */
+	/* PLLs from 0xe0 to 0xf4    */
+	struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
 
-	uint crc_plla_base;		/* _PLLA_BASE_0,	0xB0 */
-	uint crc_plla_out;		/* _PLLA_OUT_0,		0xB4 */
-	uint crc_reserved5;		/* reserved_5,		0xB8 */
-	uint crc_plla_misc;		/* _PLLA_MISC_0,	0xBC */
-
-	uint crc_pllu_base;		/* _PLLU_BASE_0,	0xC0 */
-	uint crc_reserved6;		/* _reserved_6,		0xC4 */
-	uint crc_reserved7;		/* _reserved_7,		0xC8 */
-	uint crc_pllu_misc;		/* _PLLU_MISC_0,	0xCC */
-
-	uint crc_plld_base;		/* _PLLD_BASE_0,	0xD0 */
-	uint crc_reserved8;		/* _reserved_8,		0xD4 */
-	uint crc_reserved9;		/* _reserved_9,		0xD8 */
-	uint crc_plld_misc;		/* _PLLD_MISC_0,	0xDC */
-
-	uint crc_pllx_base;		/* _PLLX_BASE_0,	0xE0 */
-	uint crc_pllx_misc;		/* _PLLX_MISC_0,	0xE4 */
-
-	uint crc_plle_base;		/* _PLLE_BASE_0,	0xE8 */
-	uint crc_plle_misc;		/* _PLLE_MISC_0,	0xEC */
-
-	uint crc_plls_base;		/* _PLLS_BASE_0,	0xF0 */
-	uint crc_plls_misc;		/* _PLLS_MISC_0,	0xF4 */
 	uint crc_reserved10;		/* _reserved_10,	0xF8 */
 	uint crc_reserved11;		/* _reserved_11,	0xFC */
 
@@ -154,46 +140,37 @@ struct clk_rst_ctlr {
 	uint crc_cpu_cmplx_clr;		/* _CPU_CMPLX_CLR_0,	0x344 */
 };
 
-#define PLL_BYPASS		(1 << 31)
-#define PLL_ENABLE		(1 << 30)
-#define PLL_BASE_OVRRIDE	(1 << 28)
-#define PLL_DIVP		(1 << 20)	/* post divider, b22:20 */
-#define PLL_DIVM		0x0C		/* input divider, b4:0 */
+/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
+#define CPU1_CLK_STP_SHIFT	9
+
+#define CPU0_CLK_STP_SHIFT	8
+#define CPU0_CLK_STP_MASK	(1U << CPU0_CLK_STP_SHIFT)
+
+/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
+#define PLL_BYPASS_SHIFT	31
+#define PLL_BYPASS_MASK		(1U << PLL_BYPASS_SHIFT)
 
-#define SWR_UARTD_RST		(1 << 1)
-#define CLK_ENB_UARTD		(1 << 1)
-#define SWR_UARTA_RST		(1 << 6)
-#define CLK_ENB_UARTA		(1 << 6)
+#define PLL_ENABLE_SHIFT	30
+#define PLL_ENABLE_MASK		(1U << PLL_ENABLE_SHIFT)
 
-#define SWR_CPU_RST		(1 << 0)
-#define CLK_ENB_CPU		(1 << 0)
-#define SWR_CSITE_RST		(1 << 9)
-#define CLK_ENB_CSITE		(1 << 9)
+#define PLL_BASE_OVRRIDE_MASK	(1U << 28)
 
-#define SET_CPURESET0		(1 << 0)
-#define SET_DERESET0		(1 << 4)
-#define SET_DBGRESET0		(1 << 12)
+#define PLL_DIVP_SHIFT		20
 
-#define SET_CPURESET1		(1 << 1)
-#define SET_DERESET1		(1 << 5)
-#define SET_DBGRESET1		(1 << 13)
+#define PLL_DIVN_SHIFT		8
 
-#define CLR_CPURESET0		(1 << 0)
-#define CLR_DERESET0		(1 << 4)
-#define CLR_DBGRESET0		(1 << 12)
+#define PLL_DIVM_SHIFT		0
 
-#define CLR_CPURESET1		(1 << 1)
-#define CLR_DERESET1		(1 << 5)
-#define CLR_DBGRESET1		(1 << 13)
+/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
+#define PLL_CPCON_SHIFT		8
+#define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
 
-#define CPU0_CLK_STP		(1 << 8)
-#define CPU1_CLK_STP		(1 << 9)
+#define PLL_LFCON_SHIFT		4
 
-#define CPCON			(1 << 8)
+#define PLLU_VCO_FREQ_SHIFT	20
 
-#define SWR_SDMMC4_RST		(1 << 15)
-#define CLK_ENB_SDMMC4		(1 << 15)
-#define SWR_SDMMC3_RST		(1 << 5)
-#define CLK_ENB_SDMMC3		(1 << 5)
+/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
+#define OSC_FREQ_SHIFT		30
+#define OSC_FREQ_MASK		(3U << OSC_FREQ_SHIFT)
 
 #endif	/* CLK_RST_H */