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| author | Thierry Reding <treding@nvidia.com> | 2015-04-21 07:18:38 +0200 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2015-05-13 09:24:16 -0700 |
| commit | 79cf644e2d330cf6fdd3ef489e44f9fb1c6f196a (patch) | |
| tree | 6acd64feb97811ee50ab957aa5688ae42b35411e /arch/arm/include/asm/arch-tegra124 | |
| parent | a0d0a594ccf54f4f430d271cab9ddb95958a9495 (diff) | |
| download | u-boot-imx-79cf644e2d330cf6fdd3ef489e44f9fb1c6f196a.zip u-boot-imx-79cf644e2d330cf6fdd3ef489e44f9fb1c6f196a.tar.gz u-boot-imx-79cf644e2d330cf6fdd3ef489e44f9fb1c6f196a.tar.bz2 | |
ARM: tegra: Enable SMMU when going non-secure
Make sure to enable the SMMU when booting the kernel in non-secure mode.
This is necessary because some of the SMMU registers are restricted to
TrustZone-secured requestors, hence the kernel wouldn't be able to turn
the SMMU on. At the same time, enable translation for all memory clients
for the same reasons. The kernel will still be able to control SMMU IOVA
translation using the per-SWGROUP enable bits.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra124')
| -rw-r--r-- | arch/arm/include/asm/arch-tegra124/mc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h b/arch/arm/include/asm/arch-tegra124/mc.h index 5557732..37998a4 100644 --- a/arch/arm/include/asm/arch-tegra124/mc.h +++ b/arch/arm/include/asm/arch-tegra124/mc.h @@ -74,6 +74,8 @@ struct mc_ctlr { u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ }; +#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) + #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) |