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author | Simon Glass <sjg@chromium.org> | 2015-08-30 16:55:28 -0600 |
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committer | Simon Glass <sjg@chromium.org> | 2015-09-02 21:28:23 -0600 |
commit | 26ad30e9d3ec445f61f94910fb14cc6e7d8efa25 (patch) | |
tree | b42ab70473504698cd6c8b095bd8c0d803ca3935 /arch/arm/include/asm/arch-rockchip | |
parent | 1f8f7730a8a3c8cc73ecb5715f5d87ed55fec541 (diff) | |
download | u-boot-imx-26ad30e9d3ec445f61f94910fb14cc6e7d8efa25.zip u-boot-imx-26ad30e9d3ec445f61f94910fb14cc6e7d8efa25.tar.gz u-boot-imx-26ad30e9d3ec445f61f94910fb14cc6e7d8efa25.tar.bz2 |
rockchip: Add basic peripheral and clock definitions
Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/include/asm/arch-rockchip')
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/clock.h | 45 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/hardware.h | 20 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-rockchip/periph.h | 54 |
3 files changed, 119 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h new file mode 100644 index 0000000..2e5ba86 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_CLOCK_H +#define _ASM_ARCH_CLOCK_H + +/* define pll mode */ +#define RKCLK_PLL_MODE_SLOW 0 +#define RKCLK_PLL_MODE_NORMAL 1 + +enum { + ROCKCHIP_SYSCON_NOC, + ROCKCHIP_SYSCON_GRF, + ROCKCHIP_SYSCON_SGRF, + ROCKCHIP_SYSCON_PMU, +}; + +/* Standard Rockchip clock numbers */ +enum rk_clk_id { + CLK_OSC, + CLK_ARM, + CLK_DDR, + CLK_CODEC, + CLK_GENERAL, + CLK_NEW, + + CLK_COUNT, +}; + +static inline int rk_pll_id(enum rk_clk_id clk_id) +{ + return clk_id - 1; +} + +/** + * rockchip_get_cru() - get a pointer to the clock/reset unit registers + * + * @return pointer to registers, or -ve error on error + */ +void *rockchip_get_cru(void); + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h new file mode 100644 index 0000000..d5af5b8 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -0,0 +1,20 @@ +/* + * Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +#define RK_CLRSETBITS(clr, set) ((((clr) | (set)) << 16) | set) +#define RK_SETBITS(set) RK_CLRSETBITS(0, set) +#define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) + +#define TIMER7_BASE 0xff810020 + +#define rk_clrsetreg(addr, clr, set) writel((clr) << 16 | (set), addr) +#define rk_clrreg(addr, clr) writel((clr) << 16, addr) +#define rk_setreg(addr, set) writel(set, addr) + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h new file mode 100644 index 0000000..fa6069b --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_PERIPH_H +#define _ASM_ARCH_PERIPH_H + +/* + * The peripherals supported by the hardware. This is used to specify clocks + * and pinctrl settings. Some SoCs will not support all of these, but it + * provides a common reference for common drivers to use. + */ +enum periph_id { + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2C0, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_UART0, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_UART4, + PERIPH_ID_LCDC0, + PERIPH_ID_LCDC1, + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_HDMI, + + PERIPH_ID_COUNT, + + /* Some aliases */ + PERIPH_ID_EMMC = PERIPH_ID_SDMMC0, + PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1, + PERIPH_ID_UART_BT = PERIPH_ID_UART0, + PERIPH_ID_UART_BB = PERIPH_ID_UART1, + PERIPH_ID_UART_DBG = PERIPH_ID_UART2, + PERIPH_ID_UART_GPS = PERIPH_ID_UART3, + PERIPH_ID_UART_EXP = PERIPH_ID_UART4, +}; + +#endif |