Merge branch 'master' of git://git.denx.de/u-boot-arm

* 'master' of git://git.denx.de/u-boot-arm: (167 commits)
  OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer
  ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT
  ARM: omap3: Set SPL stack size to 8KB, image to 54KB.
  arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx
  OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree
  omap4: do not enable auxiliary cores
  omap4: do not enable fs-usb module
  omap4: panda: disable uart2 pads during boot
  igep00x0: change mpurate from 500 to auto
  igep00x0: enable the use of a plain text file
  tegra2: trivially enable 13 mhz crystal frequency
  tegra: Enable keyboard for Seaboard
  tegra: Switch on console mux and use environment for console
  tegra: Add tegra keyboard driver
  tegra: fdt: Add keyboard definitions for Seaboard
  tegra: fdt: Add keyboard controller definition
  tegra: Add keyboard support to funcmux
  input: Add support for keyboard matrix decoding from an fdt
  input: Add generic keyboard input handler
  input: Add linux/input.h for key code support
  fdt: Add fdtdec functions to read byte array
  tegra: Enable LP0 on Seaboard
  tegra: fdt: Add EMC data for Tegra2 Seaboard
  tegra: i2c: Add function to find DVC bus
  fdt: tegra: Add EMC node to device tree
  tegra: Add EMC settings for Seaboard
  tegra: Turn off power detect in board init
  tegra: Set up warmboot code on Nvidia boards
  tegra: Setup PMC scratch info from ap20 setup
  tegra: Add warmboot implementation
  tegra: Set up PMU for Nvidia boards
  tegra: Add PMU to manage power supplies
  tegra: Add EMC support for optimal memory timings
  tegra: Add header file for APB_MISC register
  tegra: Add tegra_get_chip_type() to detect SKU
  tegra: Add flow, gp_padctl, fuse, sdram headers
  tegra: Add crypto library for warmboot code
  tegra: Add functions to access low-level Osc/PLL details
  tegra: Move ap20.h header into arch location
  Add AES crypto library
  i2c: Add TPS6586X driver
  Add abs() macro to return absolute value
  fdt: Add function to return next compatible subnode
  fdt: Add function to locate an array in the device tree
  i.MX28: Avoid redefining serial_put[cs]()
  i.MX28: Check if WP detection is implemented at all
  i.MX28: Add battery boot components to SPL
  i.MX28: Reorder battery status functions in SPL
  i.MX28: Add LRADC init to i.MX28 SPL
  i.MX28: Add LRADC register definitions
  i.MX28: Shut down the LCD controller before reset
  i.MX28: Add LCDIF register definitions
  i.MX28: Implement boot pads sampling and reporting
  i.MX28: Improve passing of data from SPL to U-Boot
  M28EVK: Add SD update command
  M28EVK: Implement support for new board V2.0
  FEC: Abstract out register setup
  MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged
  i.MX28: Add delay after CPU bypass is cleared
  spi: mxs: Allow other chip selects to work
  spi: mxs: Introduce spi_cs_is_valid()
  mx53loco: Remove unneeded gpio_set_value()
  mx53loco: Add CONFIG_REVISION_TAG
  mx53loco: Turn on VUSB regulator
  mx53loco: Add mc34708 support and set mx53 frequency at 1GHz
  pmic: dialog: Avoid name conflicts
  imx: Add u-boot.imx as target for ARM9 i.MX SOCs
  i.MX2: Include asm/types.h in arch-mx25/imx-regs.h
  imx: usb: There is no such register
  i.MX25: usb: Set PORTSCx register
  imx: nand: Support flash based BBT
  i.MX25: This architecture has a GPIO4 too
  i.MX25: esdhc: Add mxc_get_clock infrastructure
  i.MX6: mx6q_sabrelite: add SATA bindings
  i.MX6: add enable_sata_clock()
  i.MX6: Add ANATOP regulator init
  mx28evk: add NAND support
  USB: ehci-mx6: Fix broken IO access
  M28: Scan only first 512 MB of DRAM to avoid memory wraparound
  Revert "i.MX28: Enable additional DRAM address bits"
  M28: Enable FDT support
  mx53loco: Add support for 1GHz operation for DA9053-based boards
  mx53loco: Allow to print CPU information at a later stage
  mx5: Add clock config interface
  imx-common: Factor out get_ahb_clk()
  i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow
  mx31pdk: Allow booting a zImage kernel
  mx6qarm2: Allow booting a zImage kernel
  mx6qsabrelite: Allow booting a zImage kernel
  mx28evk: Allow booting a zImage kernel
  m28evk: Allow to booting a dt kernel
  mx28evk: Allow to booting a dt kernel
  mx6qsabrelite: No need to set the direction for GPIO3_23 again
  pmic: Add support for the Dialog DA9053 PMIC
  MX53: mx53loco: Add SATA support
  MX53: Add support to ESG ima3 board
  SATA: add driver for MX5 / MX6 SOCs
  MX53: add function to set SATA clock to internal
  SATA: check for return value from sata functions
  MX5: Add definitions for SATA controller
  NET: fec_mxc.c: Add a way to disable auto negotiation
  Define UART4 and UART5 base addresses
  EXYNOS: Change bits per pixel value proper for u-boot.
  EXYNOS: support TRATS board display function
  LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI
  EXYNOS: support EXYNOS MIPI DSI interface driver.
  EXYNOS: support EXYNOS framebuffer and FIMD display drivers.
  LCD: add data structure for EXYNOS display driver
  EXYNOS: add LCD and MIPI DSI clock interface.
  EXYNOS: definitions of system resgister and power management registers.
  SMDK5250: fix compiler warning
  misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998
  misc:pmic:max8997 MAX8997 support for PMIC driver
  TRATS: modify the trats's configuration
  ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement
  EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc
  arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
  arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
  cm-t35: add I2C multi-bus support
  include/configs: Remove CONFIG_SYS_64BIT_STRTOUL
  include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF
  omap3: Introduce weak misc_init_r
  omap730p2: Remove empty misc_init_r
  omap5912osk: Remove empty misc_init_r
  omap4+: Remove CONFIG_ARCH_CPU_INIT
  omap4: Remove CONFIG_SYS_MMC_SET_DEV
  OMAP3: pandora: drop console kernel argument
  OMAP3: pandora: revise GPIO configuration
  ...

6 files changed, 407 insertions, 323 deletions

diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index d0e6dd6..f32cf3e 100644
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -473,9 +473,11 @@ struct omap5_prcm_regs {
 	u32 cm_wkup_rtc_clkctrl;		/* 4ae07880 */
 	u32 pad214;				/* 4ae07884 */
 	u32 cm_wkup_bandgap_clkctrl;		/* 4ae07888 */
-	u32 pad215[197];			/* 4ae0788c */
+	u32 pad215[1];				/* 4ae0788c */
+	u32 cm_wkupaon_scrm_clkctrl;		/* 4ae07890 */
+	u32 pad216[195];
 	u32 prm_vc_val_bypass;			/* 4ae07ba0 */
-	u32 pad216[4];
+	u32 pad217[4];
 	u32 prm_vc_cfg_i2c_mode;		/* 4ae07bb4 */
 	u32 prm_vc_cfg_i2c_clk;			/* 4ae07bb8 */
 };
@@ -514,6 +516,10 @@ struct omap5_prcm_regs {
 /* CM_IDLEST_DPLL fields */
 #define ST_DPLL_CLK_MASK		1
 
+/* SGX */
+#define CLKSEL_GPU_HYD_GCLK_MASK		(1 << 25)
+#define CLKSEL_GPU_CORE_GCLK_MASK		(1 << 24)
+
 /* CM_CLKSEL_DPLL */
 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT	24
 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK		(0xFF << 24)
@@ -591,6 +597,7 @@ struct omap5_prcm_regs {
 
 /* CM_L3INIT_HSMMCn_CLKCTRL */
 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
 
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
@@ -610,36 +617,33 @@ struct omap5_prcm_regs {
 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	25
 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
 
+/* CM_WKUPAON_SCRM_CLKCTRL */
+#define OPTFCLKEN_SCRM_PER_SHIFT		9
+#define OPTFCLKEN_SCRM_PER_MASK			(1 << 9)
+#define OPTFCLKEN_SCRM_CORE_SHIFT		8
+#define OPTFCLKEN_SCRM_CORE_MASK		(1 << 8)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6
 #define OMAP_32K_CLK_FREQ		32768
 
-/* PRM_VC_CFG_I2C_CLK */
-#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT		0
-#define PRM_VC_CFG_I2C_CLK_SCLH_MASK		0xFF
-#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT		8
-#define PRM_VC_CFG_I2C_CLK_SCLL_MASK		(0xFF << 8)
-
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ	400
 
-#define PRM_VC_VAL_BYPASS_VALID_BIT	0x1000000
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT	0
-#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK	0x7F
-#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT		8
-#define PRM_VC_VAL_BYPASS_REGADDR_MASK		0xFF
-#define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
-#define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
-
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
-#define SMPS_REG_ADDR_VCORE1	0x55
-#define SMPS_REG_ADDR_VCORE2	0x5B
-#define SMPS_REG_ADDR_VCORE3	0x61
+#define SMPS_REG_ADDR_12_MPU	0x23
+#define SMPS_REG_ADDR_45_IVA	0x2B
+#define SMPS_REG_ADDR_8_CORE	0x37
+
+/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
+#define VDD_MPU		1000
+#define VDD_MM		1000
+#define VDD_CORE	1040
 
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
-#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
+/* Standard offset is 0.5v expressed in uv */
+#define PALMAS_SMPS_BASE_VOLT_UV 500000
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR		0x60
@@ -677,7 +681,7 @@ struct dpll_regs {
 	u32 cm_div_h12_dpll;
 	u32 cm_div_h13_dpll;
 	u32 cm_div_h14_dpll;
-	u32 reserved[2];
+	u32 reserved[3];
 	u32 cm_div_h22_dpll;
 	u32 cm_div_h23_dpll;
 };
@@ -700,10 +704,10 @@ extern struct omap5_prcm_regs *const prcm;
 extern const u32 sys_clk_array[8];
 
 void scale_vcores(void);
-void do_scale_tps62361(u32 reg, u32 volt_mv);
+void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
+u32 get_offset_code(u32 offset);
 u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_sri2c(void);
 void setup_post_dividers(u32 *const base, const struct dpll_params *params);
 u32 get_sys_clk_index(void);
 void enable_basic_clocks(void);
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 0697a73..8ef17c9 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -172,4 +172,15 @@ struct watchdog {
 #define OMAP_GPIO_CLEARDATAOUT		0x0190
 #define OMAP_GPIO_SETDATAOUT		0x0194
 
+/*
+ * PRCM
+ */
+
+/* PRM */
+#define PRM_BASE		0x4AE06000
+#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
+
+#define PRM_RSTCTRL		PRM_DEVICE_BASE
+#define PRM_RSTCTRL_RESET	0x01
+
 #endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
index ce1bce1..2114046 100644
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
@@ -169,6 +169,6 @@ struct hsmmc {
 #define mmc_reg_out(addr, mask, val)\
 	writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
-int omap_mmc_init(int dev_index);
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
 
 #endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
index b8c2185..4a6ed8b 100644
--- a/arch/arm/include/asm/arch-omap5/mux_omap5.h
+++ b/arch/arm/include/asm/arch-omap5/mux_omap5.h
@@ -34,7 +34,7 @@ struct pad_conf_entry {
 
 	u16 val;
 
-} __attribute__ ((__packed__));
+};
 
 #ifdef CONFIG_OFF_PADCONF
 #define OFF_PD          (1 << 12)
@@ -87,258 +87,256 @@ struct pad_conf_entry {
 #define CORE_REVISION		0x0000
 #define CORE_HWINFO		0x0004
 #define CORE_SYSCONFIG		0x0010
-#define GPMC_AD0		0x0040
-#define GPMC_AD1		0x0042
-#define GPMC_AD2		0x0044
-#define GPMC_AD3		0x0046
-#define GPMC_AD4		0x0048
-#define GPMC_AD5		0x004A
-#define GPMC_AD6		0x004C
-#define GPMC_AD7		0x004E
-#define GPMC_AD8		0x0050
-#define GPMC_AD9		0x0052
-#define GPMC_AD10		0x0054
-#define GPMC_AD11		0x0056
-#define GPMC_AD12		0x0058
-#define GPMC_AD13		0x005A
-#define GPMC_AD14		0x005C
-#define GPMC_AD15		0x005E
-#define GPMC_A16		0x0060
-#define GPMC_A17		0x0062
-#define GPMC_A18		0x0064
-#define GPMC_A19		0x0066
-#define GPMC_A20		0x0068
-#define GPMC_A21		0x006A
-#define GPMC_A22		0x006C
-#define GPMC_A23		0x006E
-#define GPMC_A24		0x0070
-#define GPMC_A25		0x0072
-#define GPMC_NCS0		0x0074
-#define GPMC_NCS1		0x0076
-#define GPMC_NCS2		0x0078
-#define GPMC_NCS3		0x007A
-#define GPMC_NWP		0x007C
-#define GPMC_CLK		0x007E
-#define GPMC_NADV_ALE		0x0080
-#define GPMC_NOE		0x0082
-#define GPMC_NWE		0x0084
-#define GPMC_NBE0_CLE		0x0086
-#define GPMC_NBE1		0x0088
-#define GPMC_WAIT0		0x008A
-#define GPMC_WAIT1		0x008C
-#define C2C_DATA11		0x008E
-#define C2C_DATA12		0x0090
-#define C2C_DATA13		0x0092
-#define C2C_DATA14		0x0094
-#define C2C_DATA15		0x0096
-#define HDMI_HPD		0x0098
-#define HDMI_CEC		0x009A
-#define HDMI_DDC_SCL		0x009C
-#define HDMI_DDC_SDA		0x009E
-#define CSI21_DX0		0x00A0
-#define CSI21_DY0		0x00A2
-#define CSI21_DX1		0x00A4
-#define CSI21_DY1		0x00A6
-#define CSI21_DX2		0x00A8
-#define CSI21_DY2		0x00AA
-#define CSI21_DX3		0x00AC
-#define CSI21_DY3		0x00AE
-#define CSI21_DX4		0x00B0
-#define CSI21_DY4		0x00B2
-#define CSI22_DX0		0x00B4
-#define CSI22_DY0		0x00B6
-#define CSI22_DX1		0x00B8
-#define CSI22_DY1		0x00BA
-#define CAM_SHUTTER		0x00BC
-#define CAM_STROBE		0x00BE
-#define CAM_GLOBALRESET		0x00C0
-#define USBB1_ULPITLL_CLK	0x00C2
-#define USBB1_ULPITLL_STP	0x00C4
-#define USBB1_ULPITLL_DIR	0x00C6
-#define USBB1_ULPITLL_NXT	0x00C8
-#define USBB1_ULPITLL_DAT0	0x00CA
-#define USBB1_ULPITLL_DAT1	0x00CC
-#define USBB1_ULPITLL_DAT2	0x00CE
-#define USBB1_ULPITLL_DAT3	0x00D0
-#define USBB1_ULPITLL_DAT4	0x00D2
-#define USBB1_ULPITLL_DAT5	0x00D4
-#define USBB1_ULPITLL_DAT6	0x00D6
-#define USBB1_ULPITLL_DAT7	0x00D8
-#define USBB1_HSIC_DATA		0x00DA
-#define USBB1_HSIC_STROBE	0x00DC
-#define USBC1_ICUSB_DP		0x00DE
-#define USBC1_ICUSB_DM		0x00E0
-#define SDMMC1_CLK		0x00E2
-#define SDMMC1_CMD		0x00E4
-#define SDMMC1_DAT0		0x00E6
-#define SDMMC1_DAT1		0x00E8
-#define SDMMC1_DAT2		0x00EA
-#define SDMMC1_DAT3		0x00EC
-#define SDMMC1_DAT4		0x00EE
-#define SDMMC1_DAT5		0x00F0
-#define SDMMC1_DAT6		0x00F2
-#define SDMMC1_DAT7		0x00F4
-#define ABE_MCBSP2_CLKX		0x00F6
-#define ABE_MCBSP2_DR		0x00F8
-#define ABE_MCBSP2_DX		0x00FA
-#define ABE_MCBSP2_FSX		0x00FC
-#define ABE_MCBSP1_CLKX		0x00FE
-#define ABE_MCBSP1_DR		0x0100
-#define ABE_MCBSP1_DX		0x0102
-#define ABE_MCBSP1_FSX		0x0104
-#define ABE_PDM_UL_DATA		0x0106
-#define ABE_PDM_DL_DATA		0x0108
-#define ABE_PDM_FRAME		0x010A
-#define ABE_PDM_LB_CLK		0x010C
-#define ABE_CLKS		0x010E
-#define ABE_DMIC_CLK1		0x0110
-#define ABE_DMIC_DIN1		0x0112
-#define ABE_DMIC_DIN2		0x0114
-#define ABE_DMIC_DIN3		0x0116
-#define UART2_CTS		0x0118
-#define UART2_RTS		0x011A
-#define UART2_RX		0x011C
-#define UART2_TX		0x011E
-#define HDQ_SIO			0x0120
-#define I2C1_SCL		0x0122
-#define I2C1_SDA		0x0124
-#define I2C2_SCL		0x0126
-#define I2C2_SDA		0x0128
-#define I2C3_SCL		0x012A
-#define I2C3_SDA		0x012C
-#define I2C4_SCL		0x012E
-#define I2C4_SDA		0x0130
-#define MCSPI1_CLK		0x0132
-#define MCSPI1_SOMI		0x0134
-#define MCSPI1_SIMO		0x0136
-#define MCSPI1_CS0		0x0138
-#define MCSPI1_CS1		0x013A
-#define MCSPI1_CS2		0x013C
-#define MCSPI1_CS3		0x013E
-#define UART3_CTS_RCTX		0x0140
-#define UART3_RTS_SD		0x0142
-#define UART3_RX_IRRX		0x0144
-#define UART3_TX_IRTX		0x0146
-#define SDMMC5_CLK		0x0148
-#define SDMMC5_CMD		0x014A
-#define SDMMC5_DAT0		0x014C
-#define SDMMC5_DAT1		0x014E
-#define SDMMC5_DAT2		0x0150
-#define SDMMC5_DAT3		0x0152
-#define MCSPI4_CLK		0x0154
-#define MCSPI4_SIMO		0x0156
-#define MCSPI4_SOMI		0x0158
-#define MCSPI4_CS0		0x015A
-#define UART4_RX		0x015C
-#define UART4_TX		0x015E
-#define USBB2_ULPITLL_CLK	0x0160
-#define USBB2_ULPITLL_STP	0x0162
-#define USBB2_ULPITLL_DIR	0x0164
-#define USBB2_ULPITLL_NXT	0x0166
-#define USBB2_ULPITLL_DAT0	0x0168
-#define USBB2_ULPITLL_DAT1	0x016A
-#define USBB2_ULPITLL_DAT2	0x016C
-#define USBB2_ULPITLL_DAT3	0x016E
-#define USBB2_ULPITLL_DAT4	0x0170
-#define USBB2_ULPITLL_DAT5	0x0172
-#define USBB2_ULPITLL_DAT6	0x0174
-#define USBB2_ULPITLL_DAT7	0x0176
-#define USBB2_HSIC_DATA		0x0178
-#define USBB2_HSIC_STROBE	0x017A
-#define UNIPRO_TX0		0x017C
-#define UNIPRO_TY0		0x017E
-#define UNIPRO_TX1		0x0180
-#define UNIPRO_TY1		0x0182
-#define UNIPRO_TX2		0x0184
-#define UNIPRO_TY2		0x0186
-#define UNIPRO_RX0		0x0188
-#define UNIPRO_RY0		0x018A
-#define UNIPRO_RX1		0x018C
-#define UNIPRO_RY1		0x018E
-#define UNIPRO_RX2		0x0190
-#define UNIPRO_RY2		0x0192
-#define USBA0_OTG_CE		0x0194
-#define USBA0_OTG_DP		0x0196
-#define USBA0_OTG_DM		0x0198
-#define FREF_CLK1_OUT		0x019A
-#define FREF_CLK2_OUT		0x019C
-#define SYS_NIRQ1		0x019E
-#define SYS_NIRQ2		0x01A0
-#define SYS_BOOT0		0x01A2
-#define SYS_BOOT1		0x01A4
-#define SYS_BOOT2		0x01A6
-#define SYS_BOOT3		0x01A8
-#define SYS_BOOT4		0x01AA
-#define SYS_BOOT5		0x01AC
-#define DPM_EMU0		0x01AE
-#define DPM_EMU1		0x01B0
-#define DPM_EMU2		0x01B2
-#define DPM_EMU3		0x01B4
-#define DPM_EMU4		0x01B6
-#define DPM_EMU5		0x01B8
-#define DPM_EMU6		0x01BA
-#define DPM_EMU7		0x01BC
-#define DPM_EMU8		0x01BE
-#define DPM_EMU9		0x01C0
-#define DPM_EMU10		0x01C2
-#define DPM_EMU11		0x01C4
-#define DPM_EMU12		0x01C6
-#define DPM_EMU13		0x01C8
-#define DPM_EMU14		0x01CA
-#define DPM_EMU15		0x01CC
-#define DPM_EMU16		0x01CE
-#define DPM_EMU17		0x01D0
-#define DPM_EMU18		0x01D2
-#define DPM_EMU19		0x01D4
-#define WAKEUPEVENT_0		0x01D8
-#define WAKEUPEVENT_1		0x01DC
-#define WAKEUPEVENT_2		0x01E0
-#define WAKEUPEVENT_3		0x01E4
-#define WAKEUPEVENT_4		0x01E8
-#define WAKEUPEVENT_5		0x01EC
-#define WAKEUPEVENT_6		0x01F0
+#define EMMC_CLK		0x0040
+#define EMMC_CMD		0x0042
+#define EMMC_DATA0		0x0044
+#define EMMC_DATA1		0x0046
+#define EMMC_DATA2		0x0048
+#define EMMC_DATA3		0x004a
+#define EMMC_DATA4		0x004c
+#define EMMC_DATA5		0x004e
+#define EMMC_DATA6		0x0050
+#define EMMC_DATA7		0x0052
+#define C2C_CLKOUT0		0x0054
+#define C2C_CLKOUT1		0x0056
+#define C2C_CLKIN0		0x0058
+#define C2C_CLKIN1		0x005a
+#define C2C_DATAIN0		0x005c
+#define C2C_DATAIN1		0x005e
+#define C2C_DATAIN2		0x0060
+#define C2C_DATAIN3		0x0062
+#define C2C_DATAIN4		0x0064
+#define C2C_DATAIN5		0x0066
+#define C2C_DATAIN6		0x0068
+#define C2C_DATAIN7		0x006a
+#define C2C_DATAOUT0		0x006c
+#define C2C_DATAOUT1		0x006e
+#define C2C_DATAOUT2		0x0070
+#define C2C_DATAOUT3		0x0072
+#define C2C_DATAOUT4		0x0074
+#define C2C_DATAOUT5		0x0076
+#define C2C_DATAOUT6		0x0078
+#define C2C_DATAOUT7		0x007a
+#define C2C_DATA8		0x007c
+#define C2C_DATA9		0x007e
+#define C2C_DATA10		0x0080
+#define C2C_DATA11		0x0082
+#define C2C_DATA12		0x0084
+#define C2C_DATA13		0x0086
+#define C2C_DATA14		0x0088
+#define C2C_DATA15		0x008a
+#define LLIA_WAKEREQOUT		0x008c
+#define LLIB_WAKEREQOUT		0x008e
+#define HSI1_ACREADY		0x0090
+#define HSI1_CAREADY		0x0092
+#define HSI1_ACWAKE		0x0094
+#define HSI1_CAWAKE		0x0096
+#define HSI1_ACFLAG		0x0098
+#define HSI1_ACDATA		0x009a
+#define HSI1_CAFLAG		0x009c
+#define HSI1_CADATA		0x009e
+#define UART1_TX		0x00a0
+#define UART1_CTS		0x00a2
+#define UART1_RX		0x00a4
+#define UART1_RTS		0x00a6
+#define HSI2_CAREADY		0x00a8
+#define HSI2_ACREADY		0x00aa
+#define HSI2_CAWAKE		0x00ac
+#define HSI2_ACWAKE		0x00ae
+#define HSI2_CAFLAG		0x00b0
+#define HSI2_CADATA		0x00b2
+#define HSI2_ACFLAG		0x00b4
+#define HSI2_ACDATA		0x00b6
+#define UART2_RTS		0x00b8
+#define UART2_CTS		0x00ba
+#define UART2_RX		0x00bc
+#define UART2_TX		0x00be
+#define USBB1_HSIC_STROBE	0x00c0
+#define USBB1_HSIC_DATA		0x00c2
+#define USBB2_HSIC_STROBE	0x00c4
+#define USBB2_HSIC_DATA		0x00c6
+#define TIMER10_PWM_EVT		0x00c8
+#define DSIPORTA_TE0		0x00ca
+#define DSIPORTA_LANE0X		0x00cc
+#define DSIPORTA_LANE0Y		0x00ce
+#define DSIPORTA_LANE1X		0x00d0
+#define DSIPORTA_LANE1Y		0x00d2
+#define DSIPORTA_LANE2X		0x00d4
+#define DSIPORTA_LANE2Y		0x00d6
+#define DSIPORTA_LANE3X		0x00d8
+#define DSIPORTA_LANE3Y		0x00da
+#define DSIPORTA_LANE4X		0x00dc
+#define DSIPORTA_LANE4Y		0x00de
+#define DSIPORTC_LANE0X		0x00e0
+#define DSIPORTC_LANE0Y		0x00e2
+#define DSIPORTC_LANE1X		0x00e4
+#define DSIPORTC_LANE1Y		0x00e6
+#define DSIPORTC_LANE2X		0x00e8
+#define DSIPORTC_LANE2Y		0x00ea
+#define DSIPORTC_LANE3X		0x00ec
+#define DSIPORTC_LANE3Y		0x00ee
+#define DSIPORTC_LANE4X		0x00f0
+#define DSIPORTC_LANE4Y		0x00f2
+#define DSIPORTC_TE0		0x00f4
+#define TIMER9_PWM_EVT		0x00f6
+#define I2C4_SCL		0x00f8
+#define I2C4_SDA		0x00fa
+#define MCSPI2_CLK		0x00fc
+#define MCSPI2_SIMO		0x00fe
+#define MCSPI2_SOMI		0x0100
+#define MCSPI2_CS0		0x0102
+#define RFBI_DATA15		0x0104
+#define RFBI_DATA14		0x0106
+#define RFBI_DATA13		0x0108
+#define RFBI_DATA12		0x010a
+#define RFBI_DATA11		0x010c
+#define RFBI_DATA10		0x010e
+#define RFBI_DATA9		0x0110
+#define RFBI_DATA8		0x0112
+#define RFBI_DATA7		0x0114
+#define RFBI_DATA6		0x0116
+#define RFBI_DATA5		0x0118
+#define RFBI_DATA4		0x011a
+#define RFBI_DATA3		0x011c
+#define RFBI_DATA2		0x011e
+#define RFBI_DATA1		0x0120
+#define RFBI_DATA0		0x0122
+#define RFBI_WE			0x0124
+#define RFBI_CS0		0x0126
+#define RFBI_A0			0x0128
+#define RFBI_RE			0x012a
+#define RFBI_HSYNC0		0x012c
+#define RFBI_TE_VSYNC0		0x012e
+#define GPIO6_182		0x0130
+#define GPIO6_183		0x0132
+#define GPIO6_184		0x0134
+#define GPIO6_185		0x0136
+#define GPIO6_186		0x0138
+#define GPIO6_187		0x013a
+#define HDMI_CEC		0x013c
+#define HDMI_HPD		0x013e
+#define HDMI_DDC_SCL		0x0140
+#define HDMI_DDC_SDA		0x0142
+#define CSIPORTC_LANE0X		0x0144
+#define CSIPORTC_LANE0Y		0x0146
+#define CSIPORTC_LANE1X		0x0148
+#define CSIPORTC_LANE1Y		0x014a
+#define CSIPORTB_LANE0X		0x014c
+#define CSIPORTB_LANE0Y		0x014e
+#define CSIPORTB_LANE1X		0x0150
+#define CSIPORTB_LANE1Y		0x0152
+#define CSIPORTB_LANE2X		0x0154
+#define CSIPORTB_LANE2Y		0x0156
+#define CSIPORTA_LANE0X		0x0158
+#define CSIPORTA_LANE0Y		0x015a
+#define CSIPORTA_LANE1X		0x015c
+#define CSIPORTA_LANE1Y		0x015e
+#define CSIPORTA_LANE2X		0x0160
+#define CSIPORTA_LANE2Y		0x0162
+#define CSIPORTA_LANE3X		0x0164
+#define CSIPORTA_LANE3Y		0x0166
+#define CSIPORTA_LANE4X		0x0168
+#define CSIPORTA_LANE4Y		0x016a
+#define CAM_SHUTTER		0x016c
+#define CAM_STROBE		0x016e
+#define CAM_GLOBALRESET		0x0170
+#define TIMER11_PWM_EVT		0x0172
+#define TIMER5_PWM_EVT		0x0174
+#define TIMER6_PWM_EVT		0x0176
+#define TIMER8_PWM_EVT		0x0178
+#define I2C3_SCL		0x017a
+#define I2C3_SDA		0x017c
+#define GPIO8_233		0x017e
+#define GPIO8_234		0x0180
+#define ABE_CLKS		0x0182
+#define ABEDMIC_DIN1		0x0184
+#define ABEDMIC_DIN2		0x0186
+#define ABEDMIC_DIN3		0x0188
+#define ABEDMIC_CLK1		0x018a
+#define ABEDMIC_CLK2		0x018c
+#define ABEDMIC_CLK3		0x018e
+#define ABESLIMBUS1_CLOCK	0x0190
+#define ABESLIMBUS1_DATA	0x0192
+#define ABEMCBSP2_DR		0x0194
+#define ABEMCBSP2_DX		0x0196
+#define ABEMCBSP2_FSX		0x0198
+#define ABEMCBSP2_CLKX		0x019a
+#define ABEMCPDM_UL_DATA	0x019c
+#define ABEMCPDM_DL_DATA	0x019e
+#define ABEMCPDM_FRAME		0x01a0
+#define ABEMCPDM_LB_CLK		0x01a2
+#define WLSDIO_CLK		0x01a4
+#define WLSDIO_CMD		0x01a6
+#define WLSDIO_DATA0		0x01a8
+#define WLSDIO_DATA1		0x01aa
+#define WLSDIO_DATA2		0x01ac
+#define WLSDIO_DATA3		0x01ae
+#define UART5_RX		0x01b0
+#define UART5_TX		0x01b2
+#define UART5_CTS		0x01b4
+#define UART5_RTS		0x01b6
+#define I2C2_SCL		0x01b8
+#define I2C2_SDA		0x01ba
+#define MCSPI1_CLK		0x01bc
+#define MCSPI1_SOMI		0x01be
+#define MCSPI1_SIMO		0x01c0
+#define MCSPI1_CS0		0x01c2
+#define MCSPI1_CS1		0x01c4
+#define I2C5_SCL		0x01c6
+#define I2C5_SDA		0x01c8
+#define PERSLIMBUS2_CLOCK	0x01ca
+#define PERSLIMBUS2_DATA	0x01cc
+#define UART6_TX		0x01ce
+#define UART6_RX		0x01d0
+#define UART6_CTS		0x01d2
+#define UART6_RTS		0x01d4
+#define UART3_CTS_RCTX		0x01d6
+#define UART3_RTS_IRSD		0x01d8
+#define UART3_TX_IRTX		0x01da
+#define UART3_RX_IRRX		0x01dc
+#define USBB3_HSIC_STROBE	0x01de
+#define USBB3_HSIC_DATA		0x01e0
+#define SDCARD_CLK		0x01e2
+#define SDCARD_CMD		0x01e4
+#define SDCARD_DATA2		0x01e6
+#define SDCARD_DATA3		0x01e8
+#define SDCARD_DATA0		0x01ea
+#define SDCARD_DATA1		0x01ec
+#define USBD0_HS_DP		0x01ee
+#define USBD0_HS_DM		0x01f0
+#define I2C1_PMIC_SCL		0x01f2
+#define I2C1_PMIC_SDA		0x01f4
+#define USBD0_SS_RX		0x01f6
 
-#define WKUP_REVISION		0x0000
-#define WKUP_HWINFO		0x0004
-#define WKUP_SYSCONFIG		0x0010
-#define PAD0_SIM_IO		0x0040
-#define PAD1_SIM_CLK		0x0042
-#define PAD0_SIM_RESET		0x0044
-#define PAD1_SIM_CD		0x0046
-#define PAD0_SIM_PWRCTRL		0x0048
-#define PAD1_SR_SCL		0x004A
-#define PAD0_SR_SDA		0x004C
-#define PAD1_FREF_XTAL_IN		0x004E
-#define PAD0_FREF_SLICER_IN	0x0050
-#define PAD1_FREF_CLK_IOREQ	0x0052
-#define PAD0_FREF_CLK0_OUT		0x0054
-#define PAD1_FREF_CLK3_REQ		0x0056
-#define PAD0_FREF_CLK3_OUT		0x0058
-#define PAD1_FREF_CLK4_REQ		0x005A
-#define PAD0_FREF_CLK4_OUT		0x005C
-#define PAD1_SYS_32K		0x005E
-#define PAD0_SYS_NRESPWRON		0x0060
-#define PAD1_SYS_NRESWARM		0x0062
-#define PAD0_SYS_PWR_REQ		0x0064
-#define PAD1_SYS_PWRON_RESET	0x0066
-#define PAD0_SYS_BOOT6		0x0068
-#define PAD1_SYS_BOOT7		0x006A
-#define PAD0_JTAG_NTRST		0x006C
-#define PAD1_JTAG_TCK		0x006D
-#define PAD0_JTAG_RTCK		0x0070
-#define PAD1_JTAG_TMS_TMSC		0x0072
-#define PAD0_JTAG_TDI		0x0074
-#define PAD1_JTAG_TDO		0x0076
-#define PADCONF_WAKEUPEVENT_0	0x007C
-#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
-#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
-#define PADCONF_MODE		0x05A8
-#define CONTROL_XTAL_OSCILLATOR			0x05AC
-#define CONTROL_CONTROL_I2C_2			0x0604
-#define CONTROL_CONTROL_JTAG			0x0608
-#define CONTROL_CONTROL_SYS			0x060C
-#define CONTROL_SPARE_RW		0x0614
-#define CONTROL_SPARE_R		0x0618
-#define CONTROL_SPARE_R_C0		0x061C
+#define LLIA_WAKEREQIN		0x0040
+#define LLIB_WAKEREQIN		0x0042
+#define DRM_EMU0		0x0044
+#define DRM_EMU1		0x0046
+#define JTAG_NTRST		0x0048
+#define JTAG_TCK		0x004a
+#define JTAG_RTCK		0x004c
+#define JTAG_TMSC		0x004e
+#define JTAG_TDI		0x0050
+#define JTAG_TDO		0x0052
+#define SYS_32K			0x0054
+#define FREF_CLK_IOREQ		0x0056
+#define FREF_CLK0_OUT		0x0058
+#define FREF_CLK1_OUT		0x005a
+#define FREF_CLK2_OUT		0x005c
+#define FREF_CLK2_REQ		0x005e
+#define FREF_CLK1_REQ		0x0060
+#define SYS_NRESPWRON		0x0062
+#define SYS_NRESWARM		0x0064
+#define SYS_PWR_REQ		0x0066
+#define SYS_NIRQ1		0x0068
+#define SYS_NIRQ2		0x006a
+#define SR_PMIC_SCL		0x006c
+#define SR_PMIC_SDA		0x006e
+#define SYS_BOOT0		0x0070
+#define SYS_BOOT1		0x0072
+#define SYS_BOOT2		0x0074
+#define SYS_BOOT3		0x0076
+#define SYS_BOOT4		0x0078
+#define SYS_BOOT5		0x007a
 
 #endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index d811d6e..e3f55d2 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -98,17 +98,6 @@
 #define TCLR_AR			(0x1 << 1)
 #define TCLR_PRE		(0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE		0x4AE06000
-#define PRM_DEVICE_BASE		(PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL		PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET	0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK	(0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE	0x0401040f
@@ -125,9 +114,10 @@
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1		0x00ffc000
 
-#define MMC1_PWRDNZ					(1 << 26)
-#define MMC1_PBIASLITE_PWRDNZ				(1 << 22)
-#define MMC1_PBIASLITE_VMODE				(1 << 21)
+#define SDCARD_PWRDNZ					(1 << 26)
+#define SDCARD_BIAS_HIZ_MODE				(1 << 25)
+#define SDCARD_BIAS_PWRDNZ				(1 << 22)
+#define SDCARD_PBIASLITE_VMODE				(1 << 21)
 
 #ifndef __ASSEMBLY__
 
@@ -136,32 +126,117 @@ struct s32ktimer {
 	unsigned int s32k_cr;	/* 0x10 */
 };
 
-struct omap4_sys_ctrl_regs {
-	unsigned int pad1[129];
-	unsigned int control_id_code;			/* 0x4A002204 */
-	unsigned int pad11[22];
-	unsigned int control_std_fuse_opp_bgap;		/* 0x4a002260 */
-	unsigned int pad2[47];
-	unsigned int control_ldosram_iva_voltage_ctrl;	/* 0x4A002320 */
-	unsigned int control_ldosram_mpu_voltage_ctrl;	/* 0x4A002324 */
-	unsigned int control_ldosram_core_voltage_ctrl;	/* 0x4A002328 */
-	unsigned int pad3[260277];
-	unsigned int control_pbiaslite;			/* 0x4A100600 */
-	unsigned int pad4[63];
-	unsigned int control_efuse_1;			/* 0x4A100700 */
-	unsigned int control_efuse_2;			/* 0x4A100704 */
+#define DEVICE_TYPE_SHIFT 0x6
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
+struct omap_sys_ctrl_regs {
+	u32 pad0[77]; /* 0x4A002000 */
+	u32 control_status; /* 0x4A002134 */
+	u32 pad1[794]; /* 0x4A002138 */
+	u32 control_paconf_global; /* 0x4A002DA0 */
+	u32 control_paconf_mode;  /* 0x4A002DA4 */
+	u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
+	u32 control_smart1io_padconf_1; /* 0x4A002DAC */
+	u32 control_smart1io_padconf_2; /* 0x4A002DB0 */
+	u32 control_smart2io_padconf_0; /* 0x4A002DB4 */
+	u32 control_smart2io_padconf_1; /* 0x4A002DB8 */
+	u32 control_smart2io_padconf_2; /* 0x4A002DBC */
+	u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
+	u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
+	u32 pad2[14];
+	u32 control_pbias; /* 0x4A002E00 */
+	u32 control_i2c_0; /* 0x4A002E04 */
+	u32 control_camera_rx; /* 0x4A002E08 */
+	u32 control_hdmi_tx_phy; /* 0x4A002E0C */
+	u32 control_uniportm; /* 0x4A002E10 */
+	u32 control_dsiphy; /* 0x4A002E14 */
+	u32 control_mcbsplp; /* 0x4A002E18 */
+	u32 control_usb2phycore; /* 0x4A002E1C */
+	u32 control_hdmi_1; /*0x4A002E20*/
+	u32 control_hsi; /*0x4A002E24*/
+	u32 pad3[2];
+	u32 control_ddr3ch1_0; /*0x4A002E30*/
+	u32 control_ddr3ch2_0; /*0x4A002E34*/
+	u32 control_ddrch1_0;	/*0x4A002E38*/
+	u32 control_ddrch1_1;	/*0x4A002E3C*/
+	u32 control_ddrch2_0;	/*0x4A002E40*/
+	u32 control_ddrch2_1;	/*0x4A002E44*/
+	u32 control_lpddr2ch1_0; /*0x4A002E48*/
+	u32 control_lpddr2ch1_1; /*0x4A002E4C*/
+	u32 control_ddrio_0;  /*0x4A002E50*/
+	u32 control_ddrio_1;  /*0x4A002E54*/
+	u32 control_ddrio_2;  /*0x4A002E58*/
+	u32 control_hyst_1; /*0x4A002E5C*/
+	u32 control_usbb_hsic_control; /*0x4A002E60*/
+	u32 control_c2c; /*0x4A002E64*/
+	u32 control_core_control_spare_rw; /*0x4A002E68*/
+	u32 control_core_control_spare_r; /*0x4A002E6C*/
+	u32 control_core_control_spare_r_c0; /*0x4A002E70*/
+	u32 control_srcomp_north_side; /*0x4A002E74*/
+	u32 control_srcomp_south_side; /*0x4A002E78*/
+	u32 control_srcomp_east_side; /*0x4A002E7C*/
+	u32 control_srcomp_west_side; /*0x4A002E80*/
+	u32 control_srcomp_code_latch; /*0x4A002E84*/
+	u32 pad4[3680198];
+	u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
+	u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
+	u32 control_padconf_mode; /* 0x4AE0CDA8 */
+	u32 control_xtal_oscillator; /* 0x4AE0CDAC */
+	u32 control_i2c_2; /* 0x4AE0CDB0 */
+	u32 control_ckobuffer; /* 0x4AE0CDB4 */
+	u32 control_wkup_control_spare_rw; /* 0x4AE0CDB8 */
+	u32 control_wkup_control_spare_r; /* 0x4AE0CDBC */
+	u32 control_wkup_control_spare_r_c0; /* 0x4AE0CDC0 */
+	u32 control_srcomp_east_side_wkup; /* 0x4AE0CDC4 */
+	u32 control_efuse_1; /* 0x4AE0CDC8 */
+	u32 control_efuse_2; /* 0x4AE0CDCC */
+	u32 control_efuse_3; /* 0x4AE0CDD0 */
+	u32 control_efuse_4; /* 0x4AE0CDD4 */
+	u32 control_efuse_5; /* 0x4AE0CDD8 */
+	u32 control_efuse_6; /* 0x4AE0CDDC */
+	u32 control_efuse_7; /* 0x4AE0CDE0 */
+	u32 control_efuse_8; /* 0x4AE0CDE4 */
+	u32 control_efuse_9; /* 0x4AE0CDE8 */
+	u32 control_efuse_10; /* 0x4AE0CDEC */
+	u32 control_efuse_11; /* 0x4AE0CDF0 */
+	u32 control_efuse_12; /* 0x4AE0CDF4 */
+	u32 control_efuse_13; /* 0x4AE0CDF8 */
 };
 
-struct control_lpddr2io_regs {
-	unsigned int control_lpddr2io1_0;
-	unsigned int control_lpddr2io1_1;
-	unsigned int control_lpddr2io1_2;
-	unsigned int control_lpddr2io1_3;
-	unsigned int control_lpddr2io2_0;
-	unsigned int control_lpddr2io2_1;
-	unsigned int control_lpddr2io2_2;
-	unsigned int control_lpddr2io2_3;
-};
+/* Output impedance control */
+#define ds_120_ohm	0x0
+#define ds_60_ohm	0x1
+#define ds_45_ohm	0x2
+#define ds_30_ohm	0x3
+#define ds_mask		0x3
+
+/* Slew rate control */
+#define sc_slow		0x0
+#define sc_medium	0x1
+#define sc_fast		0x2
+#define sc_na		0x3
+#define sc_mask		0x3
+
+/* Target capacitance control */
+#define lb_5_12_pf	0x0
+#define lb_12_25_pf	0x1
+#define lb_25_50_pf	0x2
+#define lb_50_80_pf	0x3
+#define lb_mask		0x3
+
+#define usb_i_mask	0x7
+
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN   0x80828082
+#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
+#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
+#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
+#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
+
+#define EFUSE_1 0x45145100
+#define EFUSE_2 0x45145100
+#define EFUSE_3 0x45145100
+#define EFUSE_4 0x45145100
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -169,7 +244,7 @@ struct control_lpddr2io_regs {
  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
-#define NON_SECURE_SRAM_START	0x40304000
+#define NON_SECURE_SRAM_START	0x40300000
 #define NON_SECURE_SRAM_END	0x40320000	/* Not inclusive */
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE	0x4031F000
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 40a7c57..8396a22 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -55,6 +55,8 @@ u32 omap_sdram_size(void);
 u32 cortex_rev(void);
 void init_omap_revision(void);
 void do_io_settings(void);
+void omap_vc_init(u16 speed_khz);
+int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 
 /*
  * This is used to verify if the configuration header
@@ -113,10 +115,4 @@ static inline u32 omap_hw_init_context(void)
 #endif
 }
 
-static inline u32 omap_revision(void)
-{
-	extern u32 *const omap5_revision;
-	return *omap5_revision;
-}
-
 #endif