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| author | SRICHARAN R <r.sricharan@ti.com> | 2013-02-04 04:22:02 +0000 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-03-11 11:06:10 -0400 |
| commit | 3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301 (patch) | |
| tree | eba59f79109e214726acd882ae64083641700d82 /arch/arm/include/asm/arch-omap4 | |
| parent | ee9447bfe37a646a8dce182e6f625f27c10512a0 (diff) | |
| download | u-boot-imx-3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301.zip u-boot-imx-3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301.tar.gz u-boot-imx-3fcdd4a5f8ba0e0fac4b2afdb5e90efac9f7f301.tar.bz2 | |
ARM: OMAP4+: Clean up the pmic code
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap4')
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/clocks.h | 5 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-omap4/omap.h | 3 |
2 files changed, 2 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index ceb3367..ed7a1c8 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -242,11 +242,6 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 -void scale_vcores(void); -void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv); -u32 get_offset_code(u32 offset); -void do_scale_vcore(u32 vcore_reg, u32 volt_mv); - struct omap4_scrm_regs { u32 revision; /* 0x0000 */ u32 pad00[63]; diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 1c0ce9b..73edd9d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -180,7 +180,8 @@ struct control_lpddr2io_regs { #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) #define OMAP_SRAM_SCRATCH_DPLLS_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x18) -#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP_SRAM_SCRATCH_VCORES_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x1C) +#define OMAP4_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x20) /* ROM code defines */ /* Boot device */ |