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authorAneesh V <aneesh@ti.com>2011-09-08 11:05:56 -0400
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-09-13 08:25:16 +0200
commit4ecfcfaa9ed1bb2ee73585752f9c36a12d1600c6 (patch)
tree94b5cde341423732ec4a7f7c3b0ea6d2066b5b2b /arch/arm/include/asm/arch-omap4/emif.h
parent025bc4254ba3d501cf2af49ae1d91d5b2e7c529d (diff)
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omap4: IO settings
Tuning some IO settings for better performance and power. And consolidate all such IO settings at one place. Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-omap4/emif.h')
-rw-r--r--arch/arm/include/asm/arch-omap4/emif.h18
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h
index 6845c65..3a549ba 100644
--- a/arch/arm/include/asm/arch-omap4/emif.h
+++ b/arch/arm/include/asm/arch-omap4/emif.h
@@ -593,17 +593,6 @@ struct dmm_lisa_map_regs {
u32 dmm_lisa_map_3;
};
-struct control_lpddr2io_regs {
- u32 control_lpddr2io1_0;
- u32 control_lpddr2io1_1;
- u32 control_lpddr2io1_2;
- u32 control_lpddr2io1_3;
- u32 control_lpddr2io2_0;
- u32 control_lpddr2io2_1;
- u32 control_lpddr2io2_2;
- u32 control_lpddr2io2_3;
-};
-
#define CS0 0
#define CS1 1
/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/
@@ -823,13 +812,6 @@ struct control_lpddr2io_regs {
/* MR16 value: refresh full array(no partial array self refresh) */
#define MR16_REF_FULL_ARRAY 0
-/* LPDDR2 IO regs */
-#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
-#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
-
-/* CONTROL_EFUSE_2 */
-#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
-
/*
* Maximum number of entries we keep in our array of timing tables
* We need not keep all the speed bins supported by the device