Merge branch 'master' of git://git.denx.de/u-boot-arm

Albert's rework of the linker scripts conflicted with Simon's making
everyone use __bss_end.  We also had a minor conflict over
README.scrapyard being added to in mainline and enhanced in
u-boot-arm/master with proper formatting.

Conflicts:
	arch/arm/cpu/ixp/u-boot.lds
	arch/arm/cpu/u-boot.lds
	arch/arm/lib/Makefile
	board/actux1/u-boot.lds
	board/actux2/u-boot.lds
	board/actux3/u-boot.lds
	board/dvlhost/u-boot.lds
	board/freescale/mx31ads/u-boot.lds
	doc/README.scrapyard
	include/configs/tegra-common.h

Build tested for all of ARM and run-time tested on am335x_evm.

Signed-off-by: Tom Rini <trini@ti.com>

5 files changed, 152 insertions, 1 deletions

diff --git a/arch/arm/include/asm/arch-mxs/dma.h b/arch/arm/include/asm/arch-mxs/dma.h
index a0a0ea5..1ac8696 100644
--- a/arch/arm/include/asm/arch-mxs/dma.h
+++ b/arch/arm/include/asm/arch-mxs/dma.h
@@ -40,6 +40,19 @@
 /*
  * MXS DMA channels
  */
+#if defined(CONFIG_MX23)
+enum {
+	MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP0,
+	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+	MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+	MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX28)
 enum {
 	MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
 	MXS_DMA_CHANNEL_AHB_APBH_SSP1,
@@ -53,9 +66,13 @@ enum {
 	MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
 	MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
 	MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
-	MXS_DMA_CHANNEL_AHB_APBH_SSP,
+	MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+	MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+	MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
 	MXS_MAX_DMA_CHANNELS,
 };
+#endif
 
 /*
  * MXS DMA hardware command.
diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 05eb63c..8f67497 100644
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -36,6 +36,8 @@
 #include <asm/arch/regs-rtc.h>
 #include <asm/arch/regs-ssp.h>
 #include <asm/arch/regs-timrot.h>
+#include <asm/arch/regs-usb.h>
+#include <asm/arch/regs-usbphy.h>
 
 #ifdef CONFIG_MX23
 #include <asm/arch/regs-clkctrl-mx23.h>
diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h
index 7abdf58..4288715 100644
--- a/arch/arm/include/asm/arch-mxs/iomux.h
+++ b/arch/arm/include/asm/arch-mxs/iomux.h
@@ -21,6 +21,10 @@
 #ifndef __MACH_MXS_IOMUX_H__
 #define __MACH_MXS_IOMUX_H__
 
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
 /*
  * IOMUX/PAD Bit field definitions
  *
@@ -165,4 +169,5 @@ int mxs_iomux_setup_pad(iomux_cfg_t pad);
  */
 int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
 
+#endif /* __ASSEMBLY__ */
 #endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
index 9b30f56..5920f9b 100644
--- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -74,6 +74,32 @@ struct mxs_ssp_regs {
 };
 #endif
 
+static inline int mxs_ssp_bus_id_valid(int bus)
+{
+#if defined(CONFIG_MX23)
+	const unsigned int mxs_ssp_chan_count = 2;
+#elif defined(CONFIG_MX28)
+	const unsigned int mxs_ssp_chan_count = 4;
+#endif
+
+	if (bus >= mxs_ssp_chan_count)
+		return 0;
+
+	if (bus < 0)
+		return 0;
+
+	return 1;
+}
+
+static inline int mxs_ssp_clock_by_bus(unsigned int clock)
+{
+#if defined(CONFIG_MX23)
+	return 0;
+#elif defined(CONFIG_MX28)
+	return clock;
+#endif
+}
+
 static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
 {
 	switch (port) {
diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h
index 529a3bc..f8537f1 100644
--- a/arch/arm/include/asm/arch-mxs/regs-timrot.h
+++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h
@@ -31,6 +31,16 @@
 struct mxs_timrot_regs {
 	mxs_reg_32(hw_timrot_rotctrl)
 	mxs_reg_32(hw_timrot_rotcount)
+#if defined(CONFIG_MX23)
+	mxs_reg_32(hw_timrot_timctrl0)
+	mxs_reg_32(hw_timrot_timcount0)
+	mxs_reg_32(hw_timrot_timctrl1)
+	mxs_reg_32(hw_timrot_timcount1)
+	mxs_reg_32(hw_timrot_timctrl2)
+	mxs_reg_32(hw_timrot_timcount2)
+	mxs_reg_32(hw_timrot_timctrl3)
+	mxs_reg_32(hw_timrot_timcount3)
+#elif defined(CONFIG_MX28)
 	mxs_reg_32(hw_timrot_timctrl0)
 	mxs_reg_32(hw_timrot_running_count0)
 	mxs_reg_32(hw_timrot_fixed_count0)
@@ -47,6 +57,7 @@ struct mxs_timrot_regs {
 	mxs_reg_32(hw_timrot_running_count3)
 	mxs_reg_32(hw_timrot_fixed_count3)
 	mxs_reg_32(hw_timrot_match_count3)
+#endif
 	mxs_reg_32(hw_timrot_version)
 };
 #endif
@@ -71,7 +82,11 @@ struct mxs_timrot_regs {
 #define	TIMROT_ROTCTRL_OVERSAMPLE_1X			(0x3 << 10)
 #define	TIMROT_ROTCTRL_POLARITY_B			(1 << 9)
 #define	TIMROT_ROTCTRL_POLARITY_A			(1 << 8)
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_B_MASK			(0x7 << 4)
+#elif defined(CONFIG_MX28)
 #define	TIMROT_ROTCTRL_SELECT_B_MASK			(0xf << 4)
+#endif
 #define	TIMROT_ROTCTRL_SELECT_B_OFFSET			4
 #define	TIMROT_ROTCTRL_SELECT_B_NEVER_TICK		(0x0 << 4)
 #define	TIMROT_ROTCTRL_SELECT_B_PWM0			(0x1 << 4)
@@ -79,12 +94,21 @@ struct mxs_timrot_regs {
 #define	TIMROT_ROTCTRL_SELECT_B_PWM2			(0x3 << 4)
 #define	TIMROT_ROTCTRL_SELECT_B_PWM3			(0x4 << 4)
 #define	TIMROT_ROTCTRL_SELECT_B_PWM4			(0x5 << 4)
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYA		(0x6 << 4)
+#define	TIMROT_ROTCTRL_SELECT_B_ROTARYB		(0x7 << 4)
+#elif defined(CONFIG_MX28)
 #define	TIMROT_ROTCTRL_SELECT_B_PWM5			(0x6 << 4)
 #define	TIMROT_ROTCTRL_SELECT_B_PWM6			(0x7 << 4)
 #define	TIMROT_ROTCTRL_SELECT_B_PWM7			(0x8 << 4)
 #define	TIMROT_ROTCTRL_SELECT_B_ROTARYA			(0x9 << 4)
 #define	TIMROT_ROTCTRL_SELECT_B_ROTARYB			(0xa << 4)
+#endif
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_A_MASK			0x7
+#elif defined(CONFIG_MX28)
 #define	TIMROT_ROTCTRL_SELECT_A_MASK			0xf
+#endif
 #define	TIMROT_ROTCTRL_SELECT_A_OFFSET			0
 #define	TIMROT_ROTCTRL_SELECT_A_NEVER_TICK		0x0
 #define	TIMROT_ROTCTRL_SELECT_A_PWM0			0x1
@@ -92,18 +116,25 @@ struct mxs_timrot_regs {
 #define	TIMROT_ROTCTRL_SELECT_A_PWM2			0x3
 #define	TIMROT_ROTCTRL_SELECT_A_PWM3			0x4
 #define	TIMROT_ROTCTRL_SELECT_A_PWM4			0x5
+#if defined(CONFIG_MX23)
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYA		0x6
+#define	TIMROT_ROTCTRL_SELECT_A_ROTARYB		0x7
+#elif defined(CONFIG_MX28)
 #define	TIMROT_ROTCTRL_SELECT_A_PWM5			0x6
 #define	TIMROT_ROTCTRL_SELECT_A_PWM6			0x7
 #define	TIMROT_ROTCTRL_SELECT_A_PWM7			0x8
 #define	TIMROT_ROTCTRL_SELECT_A_ROTARYA			0x9
 #define	TIMROT_ROTCTRL_SELECT_A_ROTARYB			0xa
+#endif
 
 #define	TIMROT_ROTCOUNT_UPDOWN_MASK			0xffff
 #define	TIMROT_ROTCOUNT_UPDOWN_OFFSET			0
 
 #define	TIMROT_TIMCTRLn_IRQ				(1 << 15)
 #define	TIMROT_TIMCTRLn_IRQ_EN				(1 << 14)
+#if defined(CONFIG_MX28)
 #define	TIMROT_TIMCTRLn_MATCH_MODE			(1 << 11)
+#endif
 #define	TIMROT_TIMCTRLn_POLARITY			(1 << 8)
 #define	TIMROT_TIMCTRLn_UPDATE				(1 << 7)
 #define	TIMROT_TIMCTRLn_RELOAD				(1 << 6)
@@ -121,6 +152,15 @@ struct mxs_timrot_regs {
 #define	TIMROT_TIMCTRLn_SELECT_PWM2			0x3
 #define	TIMROT_TIMCTRLn_SELECT_PWM3			0x4
 #define	TIMROT_TIMCTRLn_SELECT_PWM4			0x5
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYA		0x6
+#define	TIMROT_TIMCTRLn_SELECT_ROTARYB		0x7
+#define	TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL		0x8
+#define	TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL		0x9
+#define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xa
+#define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xc
+#elif defined(CONFIG_MX28)
 #define	TIMROT_TIMCTRLn_SELECT_PWM5			0x6
 #define	TIMROT_TIMCTRLn_SELECT_PWM6			0x7
 #define	TIMROT_TIMCTRLn_SELECT_PWM7			0x8
@@ -131,15 +171,28 @@ struct mxs_timrot_regs {
 #define	TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL		0xd
 #define	TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL		0xe
 #define	TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS		0xf
+#endif
 
+#if defined(CONFIG_MX23)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	(0xffff << 16)
+#define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	16
+#elif defined(CONFIG_MX28)
 #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK	0xffffffff
 #define	TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET	0
+#endif
 
+#if defined(CONFIG_MX23)
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffff
+#define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
+#elif defined(CONFIG_MX28)
 #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK		0xffffffff
 #define	TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET		0
+#endif
 
+#if defined(CONFIG_MX28)
 #define	TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK		0xffffffff
 #define	TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET		0
+#endif
 
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_MASK		(0xf << 16)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET		16
@@ -149,6 +202,15 @@ struct mxs_timrot_regs {
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2		(0x3 << 16)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3		(0x4 << 16)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4		(0x5 << 16)
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA		(0x6 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB		(0x7 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL		(0x8 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL		(0x9 << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xa << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xb << 16)
+#define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xc << 16)
+#elif defined(CONFIG_MX28)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5		(0x6 << 16)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6		(0x7 << 16)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7		(0x8 << 16)
@@ -159,7 +221,46 @@ struct mxs_timrot_regs {
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL		(0xd << 16)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL		(0xe << 16)
 #define	TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS		(0xf << 16)
+#endif
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_IRQ				(1 << 15)
+#define	TIMROT_TIMCTRL3_IRQ_EN				(1 << 14)
+#define	TIMROT_TIMCTRL3_DUTU_VALID			(1 << 10)
+#endif
 #define	TIMROT_TIMCTRL3_DUTY_CYCLE			(1 << 9)
+#if defined(CONFIG_MX23)
+#define	TIMROT_TIMCTRL3_POLARITY_MASK			(0x1 << 8)
+#define	TIMROT_TIMCTRL3_POLARITY_OFFSET		8
+#define	TIMROT_TIMCTRL3_POLARITY_POSITIVE		(0x0 << 8)
+#define	TIMROT_TIMCTRL3_POLARITY_NEGATIVE		(0x1 << 8)
+#define	TIMROT_TIMCTRL3_UPDATE				(1 << 7)
+#define	TIMROT_TIMCTRL3_RELOAD				(1 << 6)
+#define	TIMROT_TIMCTRL3_PRESCALE_MASK			(0x3 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_OFFSET		4
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1		(0x0 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2		(0x1 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4		(0x2 << 4)
+#define	TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8		(0x3 << 4)
+#define	TIMROT_TIMCTRL3_SELECT_MASK			0xf
+#define	TIMROT_TIMCTRL3_SELECT_OFFSET			0
+#define	TIMROT_TIMCTRL3_SELECT_NEVER_TICK		0x0
+#define	TIMROT_TIMCTRL3_SELECT_PWM0			0x1
+#define	TIMROT_TIMCTRL3_SELECT_PWM1			0x2
+#define	TIMROT_TIMCTRL3_SELECT_PWM2			0x3
+#define	TIMROT_TIMCTRL3_SELECT_PWM3			0x4
+#define	TIMROT_TIMCTRL3_SELECT_PWM4			0x5
+#define	TIMROT_TIMCTRL3_SELECT_ROTARYA		0x6
+#define	TIMROT_TIMCTRL3_SELECT_ROTARYB		0x7
+#define	TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL		0x8
+#define	TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL		0x9
+#define	TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL		0xa
+#define	TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL		0xb
+#define	TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS		0xc
+#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK	(0xffff << 16)
+#define	TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET	16
+#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK	0xffff
+#define	TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET	0
+#endif
 
 #define	TIMROT_VERSION_MAJOR_MASK			(0xff << 24)
 #define	TIMROT_VERSION_MAJOR_OFFSET			24