diff options
| author | Wolfgang Grandegger <wg@denx.de> | 2012-02-08 22:33:25 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-03-26 23:09:23 +0200 |
| commit | 3f467529cad0789b6dcc44f5ebc595c3e47341ce (patch) | |
| tree | d0624edc4bef071d11c293916797b62ec9c1579c /arch/arm/include/asm/arch-mx6 | |
| parent | 4e187fbcdf602bd6661e5fe7dc3f9c17b796dc39 (diff) | |
| download | u-boot-imx-3f467529cad0789b6dcc44f5ebc595c3e47341ce.zip u-boot-imx-3f467529cad0789b6dcc44f5ebc595c3e47341ce.tar.gz u-boot-imx-3f467529cad0789b6dcc44f5ebc595c3e47341ce.tar.bz2 | |
usb/ehci: Add USB support for the MX6Q
Currently, only USB Host 1 is supported.
Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-mx6')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 636458f..613809b 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -46,5 +46,6 @@ enum mxc_clock { u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +void enable_usboh3_clk(unsigned char enable); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 6b7589b..6a200bb 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -111,6 +111,9 @@ #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) +#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) |