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authorYe.Li <B37916@freescale.com>2014-06-11 16:15:08 +0800
committerPeng Fan <Peng.Fan@freescale.com>2015-04-29 14:43:08 +0800
commit03502475557fbea806224902056e19d478c9c6cb (patch)
tree8a56899bae959c53ad4dee7715fd75f1b3f09fee /arch/arm/include/asm/arch-mx6/imx-regs.h
parentc0e9828414fd7292ec5a84cf890d76ed675e56f0 (diff)
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ENGR00315894-58 RDC: Add an iMX platform driver for RDC-SEMA
The RDC driver provides interfaces for setting peripherals and masters at BSP initialization, before using the peripherals driver. Another interfaces for lock/unlock RDC semaphore and permission check. The driver assumes boot CPU which runs u-boot is in Domain 0 (default setting on boot). Users should not set it to other domains. The peripherals ID and masters ID may change on different chip, each should provide definitions of the IDs and be included in "imx-rdc.h". Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit 964b2672bfbec14629f5767e59e73fd3bb185e3a) Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Conflicts: arch/arm/imx-common/Makefile arch/arm/include/asm/arch-mx6/imx-regs.h
Diffstat (limited to 'arch/arm/include/asm/arch-mx6/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index e08253c..ea33a1a 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -975,6 +975,30 @@ struct mxs_lcdif_regs {
u32 hw_lcdif_as_debug5; /* 0x290 */
};
+struct rdc_regs {
+ u32 vir; /* Version information */
+ u32 reserved1[8];
+ u32 stat; /* Status */
+ u32 intctrl; /* Interrupt and Control */
+ u32 intstat; /* Interrupt Status */
+ u32 reserved2[116];
+ u32 mda[32]; /* Master Domain Assignment */
+ u32 reserved3[96];
+ u32 pdap[104]; /* Peripheral Domain Access Permissions */
+ u32 reserved4[88];
+ struct {
+ u32 mrsa; /* Memory Region Start Address */
+ u32 mrea; /* Memory Region End Address */
+ u32 mrc; /* Memory Region Control */
+ u32 mrvs; /* Memory Region Violation Status */
+ } mem_region[55];
+};
+
+struct rdc_sema_regs {
+ u8 gate[64]; /* Gate */
+ u16 rstgt; /* Reset Gate */
+};
+
#define MXS_LCDIF_BASE LCDIF2_BASE_ADDR
#define LCDIF_CTRL_SFTRST (1 << 31)