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authorFabio Estevam <fabio.estevam@freescale.com>2012-05-15 08:01:16 +0000
committerAnatolij Gustschin <agust@denx.de>2012-05-25 10:36:29 +0200
commitfff6ef72b33050344362ca441cdb6b5f9b4fb8b0 (patch)
treefdea1001ff59d86ec2cbb020a2feda4b195156a4 /arch/arm/include/asm/arch-mx5
parentf1adefd2393f0322c1c1db8e813e65d95c752cd0 (diff)
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mx53: Allow IPUv3 driver to also work on mx53
Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and mx53 SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx5')
-rw-r--r--arch/arm/include/asm/arch-mx5/imx-regs.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index cef4190..88fb7cb 100644
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -25,7 +25,8 @@
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
-#define IPU_CTRL_BASE_ADDR 0x40000000
+#define IPU_SOC_BASE_ADDR 0x40000000
+#define IPU_SOC_OFFSET 0x1E000000
#define SPBA0_BASE_ADDR 0x70000000
#define AIPS1_BASE_ADDR 0x73F00000
#define AIPS2_BASE_ADDR 0x83F00000
@@ -34,7 +35,8 @@
#define NFC_BASE_ADDR_AXI 0xCFFF0000
#define CS1_BASE_ADDR 0xB8000000
#elif defined(CONFIG_MX53)
-#define IPU_CTRL_BASE_ADDR 0x18000000
+#define IPU_SOC_BASE_ADDR 0x18000000
+#define IPU_SOC_OFFSET 0x06000000
#define SPBA0_BASE_ADDR 0x50000000
#define AIPS1_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR 0x63F00000
@@ -48,6 +50,8 @@
#error "CPU_TYPE not defined"
#endif
+#define IPU_CTRL_BASE_ADDR IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET
+
#define IRAM_SIZE 0x00020000 /* 128 KB */
/*