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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2012-08-14 11:03:59 +0000
committerTom Rini <trini@ti.com>2012-10-15 11:54:14 -0700
commitb809b3ac13e1016b2be937bd4511973f90982ad2 (patch)
treeab99f306931c72db96b6a8c38bbdb621ab494a1c /arch/arm/include/asm/arch-mx35/imx-regs.h
parentdf7e420bbd35f02604d459396134688bcb6752f3 (diff)
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mx35: Define MAX and AIPS registers
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-mx35/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-mx35/imx-regs.h52
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx35/imx-regs.h b/arch/arm/include/asm/arch-mx35/imx-regs.h
index 2c6e59c..7b09809 100644
--- a/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -314,6 +314,58 @@ struct esdc_regs {
#define ESDC_MISC_DDR_EN (1 << 8)
#define ESDC_MISC_DDR2_EN (1 << 9)
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+ u32 mpr0;
+ u32 pad00[3];
+ u32 sgpcr0;
+ u32 pad01[59];
+ u32 mpr1;
+ u32 pad02[3];
+ u32 sgpcr1;
+ u32 pad03[59];
+ u32 mpr2;
+ u32 pad04[3];
+ u32 sgpcr2;
+ u32 pad05[59];
+ u32 mpr3;
+ u32 pad06[3];
+ u32 sgpcr3;
+ u32 pad07[59];
+ u32 mpr4;
+ u32 pad08[3];
+ u32 sgpcr4;
+ u32 pad09[251];
+ u32 mgpcr0;
+ u32 pad10[63];
+ u32 mgpcr1;
+ u32 pad11[63];
+ u32 mgpcr2;
+ u32 pad12[63];
+ u32 mgpcr3;
+ u32 pad13[63];
+ u32 mgpcr4;
+ u32 pad14[63];
+ u32 mgpcr5;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+ u32 mpr_0_7;
+ u32 mpr_8_15;
+ u32 pad0[6];
+ u32 pacr_0_7;
+ u32 pacr_8_15;
+ u32 pacr_16_23;
+ u32 pacr_24_31;
+ u32 pad1[4];
+ u32 opacr_0_7;
+ u32 opacr_8_15;
+ u32 opacr_16_23;
+ u32 opacr_24_31;
+ u32 opacr_32_39;
+};
+
/*
* NFMS bit in RCSR register for pagesize of nandflash
*/