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author | Wang Huan <b18965@freescale.com> | 2014-09-05 13:52:34 +0800 |
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committer | York Sun <yorksun@freescale.com> | 2014-09-08 10:30:32 -0700 |
commit | d60a2099a20254b33a314895a4b5e6a21aebd135 (patch) | |
tree | 2fb79855edd6466a89c84cc4ce6210802aa75d06 /arch/arm/include/asm/arch-ls102xa/fsl_serdes.h | |
parent | d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6 (diff) | |
download | u-boot-imx-d60a2099a20254b33a314895a4b5e6a21aebd135.zip u-boot-imx-d60a2099a20254b33a314895a4b5e6a21aebd135.tar.gz u-boot-imx-d60a2099a20254b33a314895a4b5e6a21aebd135.tar.bz2 |
arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Jason Jin <jason.jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-ls102xa/fsl_serdes.h')
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/fsl_serdes.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h new file mode 100644 index 0000000..3a92f5a --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/fsl_serdes.h @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include <config.h> + +enum srds_prtcl { + NONE = 0, + PCIE1, + PCIE2, + SATA1, + SGMII_TSEC1, + SGMII_TSEC2, +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, +}; + +int is_serdes_configured(enum srds_prtcl device); +void fsl_serdes_init(void); +const char *serdes_clock_to_string(u32 clock); + +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); + +#endif /* __FSL_SERDES_H */ |