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| author | Vitaly Andrianov <vitalya@ti.com> | 2014-10-22 17:47:58 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-10-23 11:27:29 -0400 |
| commit | 89f44bb0ceda8ba6b96f16d84a0a8a014f251e6e (patch) | |
| tree | 73ddf2d3c066e9a52aad7b5312c651e266092bc9 /arch/arm/include/asm/arch-keystone/hardware-k2hk.h | |
| parent | 079da2d514a447626a81f9df45c9f57e2f512a77 (diff) | |
| download | u-boot-imx-89f44bb0ceda8ba6b96f16d84a0a8a014f251e6e.zip u-boot-imx-89f44bb0ceda8ba6b96f16d84a0a8a014f251e6e.tar.gz u-boot-imx-89f44bb0ceda8ba6b96f16d84a0a8a014f251e6e.tar.bz2 | |
keystone2: ecc: add ddr3 error detection and correction support
This patch adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
By default, ECC will only be enabled if RMW is supported in the
DDR EMIF controller. The entire DDR memory will be scrubbed to
zero using an EDMA channel after ECC is enabled and before
u-boot is re-located to DDR memory.
An ecc_test environment variable is added for ECC testing.
If ecc_test is set to 0, a detection of 2-bit error will reset
the device, if ecc_test is set to 1, 2-bit error detection
will not reset the device, user can still boot the kernel to
check the ECC error handling in kernel.
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-keystone/hardware-k2hk.h')
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 28de3f5..5a9ea4f 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -79,6 +79,10 @@ #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 #define KS2_DDR3B_DDRPHYC 0x02328000 +#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 + channel 29 */ + /* SGMII SerDes */ #define KS2_LANES_PER_SGMII_SERDES 4 |