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author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2015-02-20 17:04:18 +0900 |
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committer | Tom Rini <trini@ti.com> | 2015-02-21 08:23:52 -0500 |
commit | dc7de222aa82cc962f15b5d04e1e4c6b0ab62398 (patch) | |
tree | 31443e719f54f025300e213138db5e86ea35b216 /arch/arm/include/asm/arch-keystone/ddr3.h | |
parent | fd697ecf5d1797180c29328b013d48ee3a788e03 (diff) | |
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ARM: keystone: move SoC headers to mach-keystone/include/mach
Move arch/arm/include/asm/arch-keystone/*
-> arch/arm/mach-keystone/include/mach/*
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-keystone/ddr3.h')
-rw-r--r-- | arch/arm/include/asm/arch-keystone/ddr3.h | 62 |
1 files changed, 0 insertions, 62 deletions
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h deleted file mode 100644 index a22c237..0000000 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * DDR3 - * - * (C) Copyright 2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _DDR3_H_ -#define _DDR3_H_ - -#include <asm/arch/hardware.h> - -struct ddr3_phy_config { - unsigned int pllcr; - unsigned int pgcr1_mask; - unsigned int pgcr1_val; - unsigned int ptr0; - unsigned int ptr1; - unsigned int ptr2; - unsigned int ptr3; - unsigned int ptr4; - unsigned int dcr_mask; - unsigned int dcr_val; - unsigned int dtpr0; - unsigned int dtpr1; - unsigned int dtpr2; - unsigned int mr0; - unsigned int mr1; - unsigned int mr2; - unsigned int dtcr; - unsigned int pgcr2; - unsigned int zq0cr1; - unsigned int zq1cr1; - unsigned int zq2cr1; - unsigned int pir_v1; - unsigned int pir_v2; -}; - -struct ddr3_emif_config { - unsigned int sdcfg; - unsigned int sdtim1; - unsigned int sdtim2; - unsigned int sdtim3; - unsigned int sdtim4; - unsigned int zqcfg; - unsigned int sdrfc; -}; - -u32 ddr3_init(void); -void ddr3_reset_ddrphy(void); -void ddr3_init_ecc(u32 base, u32 ddr3_size); -void ddr3_disable_ecc(u32 base); -void ddr3_check_ecc_int(u32 base); -int ddr3_ecc_support_rmw(u32 base); -void ddr3_err_reset_workaround(void); -void ddr3_enable_ecc(u32 base, int test); -void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); -void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); - -#endif |