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| author | Heiko Schocher <hs@denx.de> | 2011-11-15 10:00:02 -0500 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-11-15 22:25:51 +0100 |
| commit | f3c149d6c6e5ba8dd72baa86fe527837e4fb0e9a (patch) | |
| tree | 364a65280b22137f6886a165f4a6a61e8869e10c /arch/arm/include/asm/arch-davinci/ddr2_defs.h | |
| parent | a9c1c04243154e48ba8905a5132a1191895fb1b2 (diff) | |
| download | u-boot-imx-f3c149d6c6e5ba8dd72baa86fe527837e4fb0e9a.zip u-boot-imx-f3c149d6c6e5ba8dd72baa86fe527837e4fb0e9a.tar.gz u-boot-imx-f3c149d6c6e5ba8dd72baa86fe527837e4fb0e9a.tar.bz2 | |
arm, davinci: da850/dm365 lowlevel cleanup
- Cleanup a lot of fix values, and use defines instead.
- Also make some values configurable through the board config
file.
- delete the NAND_SPL code for da850, as it is not used actually
- remove the asm code
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Wolfgang Denk <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Tom Rini <tom.rini@gmail.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-davinci/ddr2_defs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-davinci/ddr2_defs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-davinci/ddr2_defs.h b/arch/arm/include/asm/arch-davinci/ddr2_defs.h index 1b9430c..4f943b8 100644 --- a/arch/arm/include/asm/arch-davinci/ddr2_defs.h +++ b/arch/arm/include/asm/arch-davinci/ddr2_defs.h @@ -63,6 +63,7 @@ struct dv_ddr2_regs_ctrl { #define DV_DDR_SDTMR2_RASMAX_SHIFT 27 #define DV_DDR_SDTMR2_XP_SHIFT 25 +#define DV_DDR_SDTMR2_ODT_SHIFT 23 #define DV_DDR_SDTMR2_XSNR_SHIFT 16 #define DV_DDR_SDTMR2_XSRD_SHIFT 8 #define DV_DDR_SDTMR2_RTP_SHIFT 5 @@ -84,6 +85,9 @@ struct dv_ddr2_regs_ctrl { #define DV_DDR_SDCR_IBANK_SHIFT 4 #define DV_DDR_SDCR_PAGESIZE_SHIFT 0 +#define DV_DDR_SDRCR_LPMODEN (1 << 31) +#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30) + #define DV_DDR_SRCR_LPMODEN_SHIFT 31 #define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30 |