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authorTom Rini <trini@ti.com>2012-07-24 14:55:38 -0700
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-09-01 14:58:12 +0200
commitff7ec0f945d16dcd8fcb4b5347dca2770ac6cea4 (patch)
tree7d205e21a7c377231440f23501ff3538107f3540 /arch/arm/include/asm/arch-am33xx
parent87a1acbb6991521af2a8d1f75c2adacbece9ab5e (diff)
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am33xx: Use emif_regs struct for storing initialization values
Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx')
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h38
1 files changed, 4 insertions, 34 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 997480b..7806e1b 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -20,6 +20,7 @@
#define _DDR_DEFS_H
#include <asm/arch/hardware.h>
+#include <asm/emif.h>
/* AM335X EMIF Register values */
#define VTP_CTRL_READY (0x1 << 5)
@@ -49,50 +50,19 @@
#define DDR2_IOCTRL_VALUE 0x18B
/**
- * Encapsulates DDR PHY control and corresponding shadow registers.
- */
-struct ddr_phy_control {
- unsigned long reg;
- unsigned long reg_sh;
- unsigned long reg2;
-};
-
-/**
- * Encapsulates SDRAM timing and corresponding shadow registers.
- */
-struct sdram_timing {
- unsigned long time1;
- unsigned long time1_sh;
- unsigned long time2;
- unsigned long time2_sh;
- unsigned long time3;
- unsigned long time3_sh;
-};
-
-/**
- * Encapsulates SDRAM configuration.
- * (Includes refresh control registers) */
-struct sdram_config {
- unsigned long sdrcr;
- unsigned long sdrcr2;
- unsigned long refresh;
- unsigned long refresh_sh;
-};
-
-/**
* Configure SDRAM
*/
-void config_sdram(struct sdram_config *cfg);
+void config_sdram(const struct emif_regs *regs);
/**
* Set SDRAM timings
*/
-void set_sdram_timings(struct sdram_timing *val);
+void set_sdram_timings(const struct emif_regs *regs);
/**
* Configure DDR PHY
*/
-void config_ddr_phy(struct ddr_phy_control *cfg);
+void config_ddr_phy(const struct emif_regs *regs);
/**
* This structure represents the DDR registers on AM33XX devices.