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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-07-30 10:48:53 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-15 08:51:10 -0400 |
| commit | 95cb69faeb45f6396a1336bff201a50ea1677d85 (patch) | |
| tree | 6eac5c28deb7b60094ccc54ea2a1e22e92722389 /arch/arm/include/asm/arch-am33xx | |
| parent | 94d77fb656d49f2b0efe2de5605a52c5145d2c3b (diff) | |
| download | u-boot-imx-95cb69faeb45f6396a1336bff201a50ea1677d85.zip u-boot-imx-95cb69faeb45f6396a1336bff201a50ea1677d85.tar.gz u-boot-imx-95cb69faeb45f6396a1336bff201a50ea1677d85.tar.bz2 | |
ARM: AM33xx: Cleanup clocks layer
Cleaning up the clocks layer.
This helps in addition of new Soc with minimal
changes.
This is derived from OMAP4 boards.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/clock.h | 28 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 2 |
2 files changed, 26 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 703b80e..0d4b9ae 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -15,6 +15,28 @@ #define LDELAY 1000000 +/*CM_<clock_domain>__CLKCTRL */ +#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 +#define CD_CLKCTRL_CLKTRCTRL_MASK 3 + +#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 +#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 +#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 + +/* CM_<clock_domain>_<module>_CLKCTRL */ +#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 +#define MODULE_CLKCTRL_MODULEMODE_MASK 3 +#define MODULE_CLKCTRL_IDLEST_SHIFT 16 +#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) + +#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 +#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 + +#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 +#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 +#define MODULE_CLKCTRL_IDLEST_IDLE 2 +#define MODULE_CLKCTRL_IDLEST_DISABLED 3 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) @@ -77,10 +99,12 @@ extern const struct dpll_params dpll_core; extern const struct dpll_params dpll_per; extern const struct dpll_params dpll_ddr; -extern const struct cm_wkuppll *cmwkup; +extern struct cm_wkuppll *const cmwkup; -void setup_dplls(void); const struct dpll_params *get_dpll_ddr_params(void); void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *); +void prcm_init(void); +void enable_basic_clocks(void); +void do_enable_clocks(u32 *const *, u32 *const *, u8); #endif diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 683ba8e..18d7d99 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -146,8 +146,6 @@ void set_sdram_timings(const struct emif_regs *regs, int nr); */ void config_ddr_phy(const struct emif_regs *regs, int nr); -void ddr_pll_config(unsigned int ddrpll_m); - struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ |