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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2013-12-10 15:02:22 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-18 21:14:44 -0500 |
| commit | d3daba10f159cca7e9d24c6f154926a9b92c75e3 (patch) | |
| tree | 34dee6df0d4914e66bc0bc9a3c652b20fc0e7eb7 /arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | |
| parent | 965de8b91bddd1f5967240d1d44005719b09dd5e (diff) | |
| download | u-boot-imx-d3daba10f159cca7e9d24c6f154926a9b92c75e3.zip u-boot-imx-d3daba10f159cca7e9d24c6f154926a9b92c75e3.tar.gz u-boot-imx-d3daba10f159cca7e9d24c6f154926a9b92c75e3.tar.bz2 | |
ARM: AM43xx: EPOS_EVM: Add support for LPDDR2
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/hardware_am43xx.h')
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 468521b..15399dc 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -62,6 +62,7 @@ #define PRM_PER_USBPHYOCP2SCP0_CLKCTRL (CM_PER + 0x5b8) #define PRM_PER_USBPHYOCP2SCP1_CLKCTRL (CM_PER + 0x5c0) #define USBPHYOCPSCP_MODULE_EN (1 << 1) +#define CM_DEVICE_INST 0x44df4100 /* Control status register */ #define CTRL_CRYSTAL_FREQ_SRC_MASK (1 << 31) |