summaryrefslogtreecommitdiff
path: root/arch/arm/include/asm/arch-am33xx/ddr_defs.h
diff options
context:
space:
mode:
authorLokesh Vutla <lokeshvutla@ti.com>2013-12-10 15:02:23 +0530
committerTom Rini <trini@ti.com>2013-12-18 21:14:45 -0500
commitb5e01eecc89e3e5c2ed3c17b803529be3c3702fb (patch)
tree73824a5325ebcf7c0c7cfe28ac5790655f7ca2ca /arch/arm/include/asm/arch-am33xx/ddr_defs.h
parentd3daba10f159cca7e9d24c6f154926a9b92c75e3 (diff)
downloadu-boot-imx-b5e01eecc89e3e5c2ed3c17b803529be3c3702fb.zip
u-boot-imx-b5e01eecc89e3e5c2ed3c17b803529be3c3702fb.tar.gz
u-boot-imx-b5e01eecc89e3e5c2ed3c17b803529be3c3702fb.tar.bz2
ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/include/asm/arch-am33xx/ddr_defs.h')
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6af4b84..c1777df 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -136,6 +136,14 @@
#define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
#define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
+#define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
+#define DDR3_DATA0_IOCTRL_VALUE 0x84
+#define DDR3_DATA1_IOCTRL_VALUE 0x84
+#define DDR3_DATA2_IOCTRL_VALUE 0x84
+#define DDR3_DATA3_IOCTRL_VALUE 0x84
+
/**
* Configure DMM
*/