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authorFabio Estevam <fabio.estevam@freescale.com>2014-11-14 11:27:21 -0200
committerStefano Babic <sbabic@denx.de>2014-11-20 10:30:19 +0100
commit32c81ea65cc01103d3a615072690e7b5faf76656 (patch)
tree4b269b8ad31dbfa8136cd3f63cf2019bd1620868 /arch/arm/imx-common
parent53b7f18044c44e7f3ea0ee10bb4cd775df3aaa3c (diff)
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imx: consolidate set_chipselect_size function
Move MX5 specific set_chipselect_size function into generic i.MX part, such that MX6 based boards are able to use this function as well. While doing this the iomuxc gpr member needed to be consolidated between MX5 and MX6. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/imx-common')
-rw-r--r--arch/arm/imx-common/cpu.c31
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 09fc227..24740b8 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -187,3 +187,34 @@ void arch_preboot_os(void)
ipuv3_fb_shutdown();
}
#endif
+
+void set_chipselect_size(int const cs_size)
+{
+ unsigned int reg;
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ reg = readl(&iomuxc_regs->gpr[1]);
+
+ switch (cs_size) {
+ case CS0_128:
+ reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+ reg |= 0x5;
+ break;
+ case CS0_64M_CS1_64M:
+ reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+ reg |= 0x1B;
+ break;
+ case CS0_64M_CS1_32M_CS2_32M:
+ reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+ reg |= 0x4B;
+ break;
+ case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+ reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+ reg |= 0x249;
+ break;
+ default:
+ printf("Unknown chip select size: %d\n", cs_size);
+ break;
+ }
+
+ writel(reg, &iomuxc_regs->gpr[1]);
+}