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authorStefan Roese <sr@denx.de>2014-11-07 12:37:50 +0100
committerMarek Vasut <marex@denx.de>2014-12-06 13:52:46 +0100
commit881f6a448fc0005157f85bfc7c4a1d2e26bef90d (patch)
tree09a71c4a7c11dabeb2e287e3a758497034a1c13a /arch/arm/dts
parent10e8bf88c0c9ffc0af1011c7a790e792cbc67451 (diff)
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arm: socfpga: dts: Add Cadence QSPI DT node to socfpga.dtsi
This DT node is taken from the Rocketboard.org Linux repsitory. And is needed to enable (configure) the Cadence DM SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'arch/arm/dts')
-rw-r--r--arch/arm/dts/socfpga.dtsi15
-rw-r--r--arch/arm/dts/socfpga_cyclone5_socrates.dts20
2 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index bca6832..145e125 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -628,6 +628,21 @@
clock-names = "biu", "ciu";
};
+ qspi: spi@ff705000 {
+ compatible = "cadence,qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff705000 0x1000>,
+ <0xffa00000 0x1000>;
+ interrupts = <0 151 4>;
+ clocks = <&qspi_clk>;
+ ext-decoder = <0>; /* external decoder */
+ num-chipselect = <4>;
+ fifo-depth = <128>;
+ bus-num = <2>;
+ status = "disabled";
+ };
+
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index 0454108..00b1830 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -37,3 +37,23 @@
&mmc {
status = "okay";
};
+
+&qspi {
+ status = "okay";
+
+ flash0: n25q00@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00";
+ reg = <0>; /* chip select */
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ page-size = <256>;
+ block-size = <16>; /* 2^16, 64KB */
+ read-delay = <4>; /* delay value in read data capture register */
+ tshsl-ns = <50>;
+ tsd2d-ns = <50>;
+ tchsh-ns = <4>;
+ tslch-ns = <4>;
+ };
+};