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author | Michal Simek <michal.simek@xilinx.com> | 2016-04-07 15:58:23 +0200 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2016-04-13 18:29:05 +0200 |
commit | 1f4f3d33c7ba6b3d3f2d806b37e0f86cadf35885 (patch) | |
tree | 8d37fc9dc8f2e735d1ceed01145f06b115ab56c7 /arch/arm/dts/zynqmp-zcu102-revB.dts | |
parent | 52be5c05a06fc533655f63f1d1dd37b3b9e71231 (diff) | |
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ARM64: zynqmp: Add support for ZCU102 platform
Add new board support.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts/zynqmp-zcu102-revB.dts')
-rw-r--r-- | arch/arm/dts/zynqmp-zcu102-revB.dts | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts new file mode 100644 index 0000000..765108e --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -0,0 +1,42 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 RevB + * + * (C) Copyright 2016, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "zynqmp-zcu102.dts" + +/ { + model = "ZynqMP ZCU102 RevB"; +}; + +&gem3 { + phy-handle = <&phyc>; + phyc: phy@c { + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; + /* Cleanup from RevA */ + /delete-node/ phy@21; +}; + +/* Different qspi 512Mbit version */ + +/* Fix collision with u61 */ +&i2c0 { + i2cswitch@75 { + i2c@2 { + max15303@1b { /* u8 */ + compatible = "max15303"; + reg = <0x1b>; + }; + /delete-node/ max15303@20; + }; + }; +}; |