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author | Michal Simek <michal.simek@xilinx.com> | 2016-04-07 15:58:23 +0200 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2016-04-13 18:29:05 +0200 |
commit | 1f4f3d33c7ba6b3d3f2d806b37e0f86cadf35885 (patch) | |
tree | 8d37fc9dc8f2e735d1ceed01145f06b115ab56c7 /arch/arm/dts/zynqmp-clk.dtsi | |
parent | 52be5c05a06fc533655f63f1d1dd37b3b9e71231 (diff) | |
download | u-boot-imx-1f4f3d33c7ba6b3d3f2d806b37e0f86cadf35885.zip u-boot-imx-1f4f3d33c7ba6b3d3f2d806b37e0f86cadf35885.tar.gz u-boot-imx-1f4f3d33c7ba6b3d3f2d806b37e0f86cadf35885.tar.bz2 |
ARM64: zynqmp: Add support for ZCU102 platform
Add new board support.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts/zynqmp-clk.dtsi')
-rw-r--r-- | arch/arm/dts/zynqmp-clk.dtsi | 202 |
1 files changed, 202 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi new file mode 100644 index 0000000..3418909 --- /dev/null +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -0,0 +1,202 @@ +/* + * Clock specification for Xilinx ZynqMP + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&amba { + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + clk600: clk600 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + dp_aclk: clock0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-accuracy = <100>; + }; + + dp_aud_clk: clock1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + clock-accuracy = <100>; + }; + + dpdma_clk: dpdma_clk { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <533000000>; + }; + + drm_clock: drm_clock { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <262750000>; + clock-accuracy = <0x64>; + }; +}; + +&can0 { + clocks = <&clk100 &clk100>; +}; + +&can1 { + clocks = <&clk100 &clk100>; +}; + +&fpd_dma_chan1 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan2 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan3 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan4 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan5 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan6 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan7 { + clocks = <&clk600>, <&clk100>; +}; + +&fpd_dma_chan8 { + clocks = <&clk600>, <&clk100>; +}; + +&nand0 { + clocks = <&clk100 &clk100>; +}; + +&gem0 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem1 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem2 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gem3 { + clocks = <&clk125>, <&clk125>, <&clk125>; +}; + +&gpio { + clocks = <&clk100>; +}; + +&i2c0 { + clocks = <&clk100>; +}; + +&i2c1 { + clocks = <&clk100>; +}; + +&qspi { + clocks = <&clk300 &clk300>; +}; + +&sata { + clocks = <&clk250>; +}; + +&sdhci0 { + clocks = <&clk200 &clk200>; +}; + +&sdhci1 { + clocks = <&clk200 &clk200>; +}; + +&spi0 { + clocks = <&clk200 &clk200>; +}; + +&spi1 { + clocks = <&clk200 &clk200>; +}; + +&uart0 { + clocks = <&clk100 &clk100>; +}; + +&uart1 { + clocks = <&clk100 &clk100>; +}; + +&usb0 { + clocks = <&clk250>, <&clk250>; +}; + +&usb1 { + clocks = <&clk250>, <&clk250>; +}; + +&xilinx_drm { + clocks = <&drm_clock>; +}; + +&xlnx_dp { + clocks = <&dp_aclk>, <&dp_aud_clk>; +}; + +&xlnx_dpdma { + clocks = <&dpdma_clk>; +}; + +&xlnx_dp_snd_codec0 { + clocks = <&dp_aud_clk>; +}; |